SLVSHP0 July   2024 TLVM14404 , TLVM14406

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  CONFIG Device Configuration Pin
      4. 7.3.4  Adjustable Switching Frequency
      5. 7.3.5  Adjustable Output Voltage (FB)
      6. 7.3.6  Input Capacitors
      7. 7.3.7  Output Capacitors
      8. 7.3.8  Power-Good Output Voltage Monitoring
      9. 7.3.9  Bias Supply Regulator (VCC, VOSNS)
      10. 7.3.10 Overcurrent Protection (OCP)
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High-efficiency, Dual Output 5V at 3A, 3.3V at 3A, Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – High-efficiency, 6A, Synchronous Buck Regulator for Industrial Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 Switching Frequency Selection
          3. 8.2.2.2.3 Input Capacitor Selection
          4. 8.2.2.2.4 Output Capacitor Selection
          5. 8.2.2.2.5 Other Connections
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.9 Bias Supply Regulator (VCC, VOSNS)

VCC is the output of the internal LDO sub-regulator used to supply the control circuits of the TLVM1440x. The nominal VCC voltage is 3.3V. The VOSNS pin is the input to the internal LDO. Connect this input to VOUT to provide the lowest possible input supply current. If the VOSNS voltage is less than 3.1V, VIN1 and VIN2 directly power the internal LDO.

To prevent unsafe operation, VCC has UVLO protection that prevents switching if the internal voltage is too low. See VCC_UVLO and VCC_UVLO_HYS in the Electrical Characteristics.

VCC must not be used to power external circuitry. Do not load VCC or short VCC to ground. VOSNS is an optional input to the internal LDO. Connect an optional high quality 0.1µF to 1µF capacitor from VOSNS to AGND for improved noise immunity.

The LDO provides the VCC voltage from one of two inputs: VIN or VOSNS. When VOSNS is tied to ground or below 3.1V, the LDO derives power from VIN. The LDO input becomes VOSNS when VOSNS is tied to a voltage above 3.1V. The VOSNS voltage must not exceed both VIN and 12V.

Equation 8 specifies the LDO power loss reduction as:

Equation 8. PLDO-LOSS=ILDO×VVOSNS-VVCC

The VOSNS input provides an option to supply the LDO with a lower voltage than VIN, thus minimizing the LDO input voltage relative to VCC and reducing power loss. For example, if the LDO current is 10mA at 1MHz with VIN = 24V and VOUT = 5V, the LDO power loss with VOSNS tied to ground is 10mA × (24V – 3.3V) = 207mW, while the loss with VOSNS tied to VOUT is equal to 10mA × (5V – 3.3V) = 17mW – a reduction of 190mW.