SLVSHP0 July 2024 TLVM14404 , TLVM14406
PRODUCTION DATA
RCH package, 28-pin QFN-FCMOD with Wettable Flanks
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NO. | NAME | |||
DUAL OUTPUT | SINGLE OUTPUT | |||
14 | VIN2 | VIN2 | I | Input supply to the regulator. Connect a high quality bypass capacitors from this pin to PGND. Low impedance connection must be provided to VIN1. |
15 | BOOT2 | BOOT2 | I/O | Channel 2 high-side driver upper supply rail. Connected to an internal 100nF capacitor between SW2 and BOOT2. An internal diode charges the capacitor while SW2 is low. Mechanical connection, use as NC in design. |
16, 17 | SW2 | SW2 | P | Channel 2 Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Mechanical connection, use as NC in design. |
22, 23 | SW1 | SW1 | P | Channel 1 Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Mechanical connection, use as NC in design. |
24 | BOOT1 | BOOT1 | I/O | Channel 1 High-side driver upper supply rail. Connected to an internal 100nF between SW1 and BOOT1. An internal diode charges the capacitor while SW1 is low. Mechanical connection, use as NC in design. |
25 | VIN1 | VIN1 | I | Input supply to the regulator. Connect a high quality bypass capacitors from this pin to PGND. Low impedance connection must be provided to VIN2. |
27 | GND | GND | G | Analog ground connection. Ground return for the internal logic. |
1 | PG1 | PG1 | O | Dual function pin. An open drain output that transitions low if VOSNS1 is outside a specified regulation window in dual output and single output primary configuration. |
2 | EN1 | EN1 | I | An active high input TLVM1440x (VOH > 1.375V) enables Output 1 in dual output operation. When in single output operation, an active high input enables all phases in the system. When disabled, the TLVM1440x is in shutdown mode. EN1 must never be floating. |
3 | BIAS & VOSNS1 | BIAS & VOSNS1 | I | Output voltage sense and input to internal voltage regulator. Connect to non-switching side of the inductor. Connect an optional high quality 0.1μF capacitor from this pin to AGND for best performance. |
4 | FB1 | FB1 | I | Feedback input to channel 1 of the TLVM1440x in dual output operation and feedback input to all channels in single output operation. Connect FB1 to VCC through a 10kΩ resistor for a 5V output or connect FB1 to AGND for a 3.3V output. A resistive divider from the non-switching side of the inductor to FB1 sets the output voltage level between 0.8V and 20V. The regulation threshold at FB1 is 0.8V. For lower output voltages use at least a 10kΩ for the top of the resistor divider. |
5 | VCC | VCC | O | Internal regulator output. Used as supply to internal control circuits. Do not connect to any external loads. Connect a high quality 1μF capacitor from this pin to AGND. |
6 | AGND | AGND | G | Analog ground connection. Ground return for the internal voltage reference and analog circuits. |
7 | RT | RT | I | Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100kHz and 2.2MHz. |
8 | FB2 | SS | I | Dual function pin. When in dual output operation, the pin functions as FB2, feedback input to channel 2 of the TLVM1440x. Connect FB2 to VCC through a 10kΩ resistor for a 5V output or connect FB2 to AGND for a 3.3V output. A resistive divider from the non-switching side of the inductor to FB2 sets the output voltage level between 0.8V and 20V. For lower output voltages use at least a 10kΩ for the top of the resistor divider. When in single output mode, the pin functions as SS. An external capacitor must be placed from SS to AGND for external soft start of the output. Connect the SS pins of primary and secondaries for fault communication between devices. |
9 | VOSNS2 | COMP | I | Dual function pin. In dual output operation, the pin functions as VOSNS2 for the fixed 3.3V and 5V and adjustable output conditions. In single output operation, the pin is the output of the internal error amplifier. |
10 | EN2 | EN2 | I | An active high input (VOH > 1.375V) enables Output 2 in dual output operation. When in single output mode, EN2 of all TLVM1440x must be connected together. An active high input enables all secondary phases in the system. When disabled, only one channel in the primary TLVM1440x is active while all remaining phases are in shutdown mode. EN2 must never be floating. |
11 | CONFIG | CONFIG | I | Single or Dual output selection. Connect specific resistor values to the pin (refer to Table 7-1) to select number of phases, primary and secondary and dither options. |
12 | PG2 | NC | O | Dual function pin. In dual output operation, this pin behaves as PG2, an open drain output that transitions low if VOSNS2 is outside a specified regulation window. In single output mode, leave the pin floating. |
18, 19 | VOUT2 | VOUT | O | Output of module. Connect a high quality bypass capacitors from this pin to PGND. |
20, 21 | VOUT1 | VOUT | O | Output of module. Connect a high quality bypass capacitors from this pin to PGND. |
13. 26 | PGND | PGND | G | Power ground to internal low side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND1, PGND3 and PGND4. Connect a high quality bypass capacitors from this pin to VIN2. |
28 | PGND | PGND | G | Power ground and heat sink connection. Solder directly to system ground plane. Low impedance connection must be provided to other PGND pins. |