The following list summarizes the essential
guidelines for PCB layout and component placement to optimize DC/DC module
performance, including thermals and EMI signature. Figure 8-24
shows a recommended PCB layout for the TLVM1440x with
optimized placement and routing of the power-stage and small-signal components.
- Place input capacitors as close as possible to the VIN pins. Note the dual and symmetrical arrangement of the input capacitors based on the VIN1 and VIN2 pins located on each side of the module package. The high-frequency currents are split in two and effectively flow in opposing directions such that the related magnetic fields contributions cancel each other, leading to improved EMI performance.
- Use low-ESR 1206 or 1210 ceramic capacitors with X7R or X7S dielectric. The module has integrated dual 0402 input capacitors for high-frequency bypass.
- Ground return paths for the input capacitors must consist of localized top-side planes that connect to the PGND pads under the module.
- Use a wide polygon plane on a lower PCB layer to
connect these pins together and to the input supply, even though the VIN
pins are connected internally
- Place output capacitors as close as possible to the VOUT pins. A similar dual and symmetrical arrangement of the output capacitors enables magnetic field cancellation and EMI mitigation.
- Make sure ground return paths for the output
capacitors consist of localized top-side planes that connect to the PGND
pads under the module.
- Use a wide polygon plane on a lower PCB layer to
connect these pins together and to the load, thus reducing conduction
loss and thermal stress, even though the VOUT pins are connected
internally
- Keep the FB trace as short as possible by
placing the feedback resistors close to the FB pin. Reduce noise
sensitivity of the output voltage feedback path by placing the resistor divider
close to the FB pin, rather than close to the load. FB is the input to the
voltage-loop error amplifier and represents a high-impedance node sensitive to
noise. Route a trace from the upper feedback resistor to the required point of
output voltage regulation.
- Use a solid ground plane on the PCB layer directly below the top layer with the module. This plane acts as a noise shield by minimizing the magnetic fields associated with the currents in the switching loops. Connect AGND pins 6 and 11 directly to PGND pin 19 under the module.
- Provide enough PCB area for proper heat
sinking. Use sufficient copper area to achieve a low thermal impedance
commensurate with the maximum load current and ambient temperature conditions.
Provide adequate heat sinking for the TLVM1440x to
keep the junction temperature below 150°C. For operation at full rated load, the
top-side ground plane is an important heat-dissipating area. Use an array of
heat-sinking vias to connect the exposed pads (PGND) of the package to the PCB
ground plane. If the PCB has multiple copper layers, connect these thermal vias
to inner-layer ground planes. Make the top and bottom PCB layers preferably with
two-ounce copper thickness (and no less than one ounce).