SNVSCN6 December   2023 TLVM365R1 , TLVM365R15

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Shutdown, and Start-Up
      2. 7.3.2  Adjustable Switching Frequency (With RT)
      3. 7.3.3  Power-Good Output Operation
      4. 7.3.4  Internal LDO, VCC UVLO, and VOUT/FB Input
      5. 7.3.5  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      6. 7.3.6  Output Voltage Selection
      7. 7.3.7  Soft Start and Recovery from Dropout
        1. 7.3.7.1 Soft Start
        2. 7.3.7.2 Recovery from Dropout
      8. 7.3.8  Current Limit and Short Circuit
      9. 7.3.9  Thermal Shutdown
      10. 7.3.10 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode - Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 Minimum On-time Operation
        4. 7.4.3.4 Dropout
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Choosing the Switching Frequency
        3. 8.2.2.3  Setting the Output Voltage
        4. 8.2.2.4  Input Capacitor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  VCC
        7. 8.2.2.7  CFF Selection
        8. 8.2.2.8  External UVLO
        9. 8.2.2.9  Power-Good Signal
        10. 8.2.2.10 Maximum Ambient Temperature
        11. 8.2.2.11 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power-Good Output Operation

Use the power-good feature using the PGOOD pin of the TLVM365R1x to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output remains low under device fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for any short duration excursions in the output voltage, such as during line and load transients. Output voltage excursions lasting less than tRESET_FILTER do not trip the power-good flag. Power-good operation can best be understood in reference to Figure 7-4. Table 7-2 gives a more detailed breakdown the PGOOD operation. Here, VPG-UV is defined as the PG-UV scaled version of the VOUT-Reg (target regulated output voltage) and VPG-HYS as the PG-HYS scaled version of the VOUT-Reg, where both PG-UV and PG-HYS are listed in Section 6.5. During the initial power up, a total delay of 5 ms (typical) is encountered from the time the VEN-VOUT is triggered to the time that the power-good is flagged high. This delay only occurs during the device start-up and is not encountered during any other normal operation of the power-good function. When EN/UVLO is pulled low, the power-good flag output is also forced low. With EN/UVLO low, power good remains valid as long as the input voltage (VPG-VALID is ≥ 0.9 V (typical)).

The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup resistor connected to a suitable logic supply. The power-good output scheme can also be pulled up to either VCC or VOUT through an appropriate resistor, as desired. If this function is not needed, the PGOOD pin can be open or grounded. Limit the current into this pin to ≤ 4 mA.

GUID-6D77F38A-3707-40F5-A69F-83D834310502-low.gif Figure 7-4 Power-Good Operation (OV Events Not Included)
Table 7-2 Fault Conditions for PGOOD (Pull Low)
FAULT CONDITION INITIATED FAULT CONDITION ENDS (AFTER WHICH tPGOOD_ACT MUST PASS BEFORE PGOOD OUTPUT IS RELEASED)
VOUT < VPG-UV AND t > tRESET_FILTER Output voltage in regulation:
VPG-UV + VPG-HYS < VOUT < VPG-OV – VPG-HYS
VOUT > VPG-OV AND t > tRESET_FILTER Output voltage in regulation
TJ > TSD-R TJ < TSD-F and output voltage in regulation
EN < VEN-VOUT – VEN-HYST EN > VEN-VOUT and output voltage in regulation
VCC < VCC-UVLO – VCC-UVLO-HYST VCC > VCC-UVLO and output voltage in regulation