SNVSCN6 December   2023 TLVM365R1 , TLVM365R15

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Shutdown, and Start-Up
      2. 7.3.2  Adjustable Switching Frequency (With RT)
      3. 7.3.3  Power-Good Output Operation
      4. 7.3.4  Internal LDO, VCC UVLO, and VOUT/FB Input
      5. 7.3.5  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      6. 7.3.6  Output Voltage Selection
      7. 7.3.7  Soft Start and Recovery from Dropout
        1. 7.3.7.1 Soft Start
        2. 7.3.7.2 Recovery from Dropout
      8. 7.3.8  Current Limit and Short Circuit
      9. 7.3.9  Thermal Shutdown
      10. 7.3.10 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode - Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 Minimum On-time Operation
        4. 7.4.3.4 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Choosing the Switching Frequency
        3. 8.2.2.3  Setting the Output Voltage
        4. 8.2.2.4  Input Capacitor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  VCC
        7. 8.2.2.7  CFF Selection
        8. 8.2.2.8  External UVLO
        9. 8.2.2.9  Power-Good Signal
        10. 8.2.2.10 Maximum Ambient Temperature
        11. 8.2.2.11 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Thermal Information

THERMAL METRIC(1) TLVM365R15 / TLVM365R1 UNIT
RDN
11 PINS
RθJA Junction-to-ambient thermal resistance (2) 42.9 °C/W
ψJT Junction-to-top characterization parameter (3) 4.4 °C/W
ψJB Junction-to-board characterization parameter (4) 17.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 
(2) The value of RθJA given in this table is valid for comparison with other packages and can not be used for design purposes. This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. It does not represent the performance obtained in an actual application. 
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (section 6 and 7). TJ = ψJT ∙ Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. 
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (section 6 and 7). TJ = ψJB ∙ Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1-mm from the device.