SLYS053B November 2023 – June 2024 TMAG3001
PRODUCTION DATA
For a read operation the controller sends a START condition, followed by the target address with the R/W bit set to 0b (signifying a write). The target acknowledges the write request, and the controller sends the control byte with the Conversion Trigger bit and Register Pointer Address. After the Control Register, the controller will initiate a restart followed by the target address with the R/W bit set to 1b (signifying a read). The controller will continue to send out clock pulses but releases the SDA line so that the target can transmit data. At the end of every byte of data, the controller sends an ACK to the target, letting the target know that the controller is ready for more data. After the controller has received the number of bytes the controller expected, the controller sends a NACK, signaling to the target to halt communications and release the SDA line. The controller follows this up with a STOP condition.