SLYS053B November   2023  – June 2024 TMAG3001

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Temperature Sensor
    7. 5.7  Magnetic Characteristics For A1
    8. 5.8  Magnetic Characteristics For A2
    9. 5.9  Magnetic Temp Compensation Characteristics
    10. 5.10 I2C Interface Timing
    11. 5.11 Power up Timing
    12. 5.12 Timing Diagram
    13. 5.13 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Magnetic Flux Direction
      2. 6.3.2 Sensor Location
      3. 6.3.3 Interrupt Function
      4. 6.3.4 Wake on Change
      5. 6.3.5 Device I2C Address
      6. 6.3.6 Magnetic Range Selection
      7. 6.3.7 Update Rate Settings
    4. 6.4 Device Functional Modes
      1. 6.4.1 Standby (Trigger) Mode
      2. 6.4.2 Sleep Mode
      3. 6.4.3 Wake-Up and Sleep (W&S) Mode
      4. 6.4.4 Continuous Measure Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Interface
        1. 6.5.1.1 Conversion Trigger
        2. 6.5.1.2 Bus Transactions
          1. 6.5.1.2.1 Three Channels I2C Write
          2. 6.5.1.2.2 General Call Write
          3. 6.5.1.2.3 Standard I2C Read
          4. 6.5.1.2.4 I2C Read Command for 16-bit Data
          5. 6.5.1.2.5 I2C Read Command for 8-Bit Data
          6. 6.5.1.2.6 I2C Read CRC
      2. 6.5.2 Data Definition
        1. 6.5.2.1 Magnetic Sensor Data
        2. 6.5.2.2 Temperature Sensor Data
        3. 6.5.2.3 Magnetic Sensor Gain Correction
        4. 6.5.2.4 Magnetic Sensor Offset Correction
        5. 6.5.2.5 Angle and Magnitude Data Definition
        6. 6.5.2.6 Angle Offset Correction
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Select the Sensitivity Option
      2. 7.1.2 Temperature Compensation for Magnets
      3. 7.1.3 Sensor Conversion
        1. 7.1.3.1 Continuous Conversion
        2. 7.1.3.2 Trigger Conversion
        3. 7.1.3.3 Pseudo-Simultaneous Sampling
      4. 7.1.4 Magnetic Limit Check
      5. 7.1.5 Magnitude Limit Check
      6. 7.1.6 Angle Limit Check
      7. 7.1.7 Switch Mode
        1. 7.1.7.1 Unipolar Switch Mode
        2. 7.1.7.2 Omnipolar Switch Mode
        3. 7.1.7.3 Tamper Detection
        4. 7.1.7.4 Angle Switch
        5. 7.1.7.5 Magnitude Switch (Button Press Detection)
      8. 7.1.8 Error Calculation During Linear Measurement
      9. 7.1.9 Error Calculation During Angular Measurement
    2. 7.2 Typical Application
      1. 7.2.1 Angle Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Gain Adjustment for Angle Measurement
        3. 7.2.1.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. Register Map
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

I2C Interface

The TMAG3001 has a standard bidirectional I2C interface that is controlled by a controller device to be configured or read the status of the device. Each target on the I2C bus has a specific device address to differentiate between other target devices that are on the same I2C bus. Many target devices require configuration upon start-up to set the behavior of the device. This is typically done when the controller accesses internal register maps of the target, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. At the start bit of an I2C transaction, the conversion result registers are locked to the most recent completed conversion to prevent the results from changing mid transaction. If a conversion is completed mid I2C transaction, the device updates the results register with the new values immediately after the stop condition. The TMAG3001 supports transmission data rates up to 1MHz.

The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to a supply through a pullup resistor. The size of the pullup resistor is determined by the amount of capacitance on the I2C lines and the communication frequency. For further details, see the I2C Pullup Resistor Calculation application report. Data transfer can only be initiated when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition.

The following is the general procedure for a controller to access a target device:

  1. If a controller wants to send data to a target:
    • Controller-transmitter sends a START condition and addresses the target-receiver.
    • Controller-transmitter sends the requested register to write target-receiver.
    • Controller-transmitter sends data to target-receiver.
    • Controller-transmitter terminates the transfer with a STOP condition.
  2. If a controller wants to receive or read data from a target:
    • Controller-receiver sends a START condition and addresses the target-transmitter.
    • Controller-receiver sends the requested register to read to target-transmitter.
    • Controller-receiver sends a RESTART condition and addresses the target-transmitter.
    • Controller-receiver receives data from the target-transmitter.
    • Controller-receiver terminates the transfer with a STOP condition.
TMAG3001 Definition of Start and Stop Conditions Figure 6-11 Definition of Start and Stop Conditions
TMAG3001 Bit Transfer Figure 6-12 Bit Transfer