SLYS052A March 2023 – December 2023 TMAG5170D-Q1
PRODUCTION DATA
This diagnostic mechanism for every SPI transaction will compute the CRC of the received SPI frame from the controller and check the CRC against the CRC value transmitted by the controller, and flag a fault if the values do not match. The device also embeds a CRC value as part of the SPI frame in the response for the controller to check the integrity of the received data. This check detects faults with the SPI communication block in the digital core, the SPI I/O buffers and, and the controller to check for any faults on the SPI external to the device.
Another check also runs in the background that counts the number of SPI clocks in a SPI frame and flags a fault if the number of clocks sent by the controller is not same as the expected value. This can help the controller detect any issues with the SPI.
Run Mode | Continuous, every time a SPI transaction is initiated |
Configuration Register(s) | CRC_DIS to disable CRC in the SPI protocol |
Fault Register Bit | CRC_STAT, FRAME_STAT |
Impact if disabled | If CRC is disabled, then any fault with SPI communication will not be detected and incorrect value of measured field can be reported. |