SLYS052A March 2023 – December 2023 TMAG5170D-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SPI Interface | ||||||
fSPI | SPI clock (SCK) frequency | CL = 25 pF VCC = 2.3 V to 3.0 V |
8 | MHz | ||
fSPI | SPI clock (SCK) frequency | CL = 25 pF VCC = 3.0 V to 5.5 V |
10 | MHz | ||
twhigh | High time: SCK logic high time duration | 45 | ns | |||
twlow | Low time: SCK logic low time duration | 45 | ns | |||
tsu_cs | CS setup time: Time delay between falling edge of CS and rising edge of SCK | 45 | ns | |||
th_cs | Hold time: Time between the falling edge of SCK and rising edge of CS | 45 | ns | |||
tpd_soen | Delay time: Time delay from falling edge of CS to data valid at SDO | 45 | ns | |||
tpd_sodis | Delay time: Time delay from rising edge of CS to SDO transition to high-impedance | 55 | ns | |||
tsu_si | SDI setup time: Setup time of SDI before the rising edge of SCK | 25 | ns | |||
th_si | Hold time: Time between the rising edge of SCK to SDI valid | 25 | ns | |||
tpd_so | Propagation delay from falling edge of SCK to SDO | 45 | ns | |||
tw_cs | SPI transfer inactive time (time between two transfers) during which CS must remain high. | CL = 25 pF | 100 | ns | ||
tspi_deep_sleep | Setup time between CS going low and SCK start during deep sleep mode | 150 | 320 | µs |