SLYS035A September   2022  – September 2023 TMAG5173-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Temperature Sensor
    7. 6.7  Magnetic Characteristics For A1, B1, C1, D1
    8. 6.8  Magnetic Characteristics For A2, B2, C2, D2
    9. 6.9  Magnetic Temp Compensation Characteristics
    10. 6.10 I2C Interface Timing
    11. 6.11 Power up Timing
    12. 6.12 Timing Diagram
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Magnetic Flux Direction
      2. 7.3.2 Sensor Location
      3. 7.3.3 Interrupt Function
      4. 7.3.4 Device I2C Address
      5. 7.3.5 Magnetic Range Selection
      6. 7.3.6 Update Rate Settings
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby (Trigger) Mode
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Continuous Measure Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 SCL
        2. 7.5.1.2 SDA
        3. 7.5.1.3 I2C Read/Write
          1. 7.5.1.3.1 Standard I2C Write
          2. 7.5.1.3.2 General Call Write
          3. 7.5.1.3.3 Standard 3-Byte I2C Read
          4. 7.5.1.3.4 1-Byte I2C Read Command for 16-Bit Data
          5. 7.5.1.3.5 1-Byte I2C Read Command for 8-Bit Data
          6. 7.5.1.3.6 I2C Read CRC
      2. 7.5.2 Data Definition
        1. 7.5.2.1 Magnetic Sensor Data
        2. 7.5.2.2 Temperature Sensor Data
        3. 7.5.2.3 Angle and Magnitude Data Definition
        4. 7.5.2.4 Magnetic Sensor Offset Correction
    6. 7.6 TMAG5173-Q1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Select the Sensitivity Option
      2. 8.1.2 Temperature Compensation for Magnets
      3. 8.1.3 Sensor Conversion
        1. 8.1.3.1 Continuous Conversion
        2. 8.1.3.2 Trigger Conversion
        3. 8.1.3.3 Pseudo-Simultaneous Sampling
      4. 8.1.4 Magnetic Limit Check
      5. 8.1.5 Magnetic Threshold Band Cross Detection
      6. 8.1.6 Error Calculation During Linear Measurement
      7. 8.1.7 Error Calculation During Angular Measurement
    2. 8.2 Typical Applications
      1. 8.2.1 Angle Measurement
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Gain Adjustment for Angle Measurement
        3. 8.2.1.3 Application Curves
      2. 8.2.2 I2C Address Expansion
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 I2C Interface Timing

minimum and maximum specifications are over –40°C to 125°C and VCC = 2.3 V to 3.6 V (unless otherwise noted)(1)
FAST MODE FAST MODE PLUS UNIT
MIN MAX MIN MAX
f(SCL) SCL operating frequency 1 400 1 1000 kHz
t(BUF) Bus-free time between STOP and START conditions 1.3 0.5 µs
t(SUSTA) Repeated START condition setup time 0.6 0.26 µs
t(HDSTA) Hold time after repeated START condition.
After this period, the first clock is generated.		 0 0 µs
t(SUSTO) STOP condition setup time 0.6 0.26 µs
t(HDDAT) Data hold time(2) 0 900 0 150 ns
t(SUDAT) Data setup time 100 50 ns
t(LOW) SCL clock low period 1.3 0.5 µs
t(HIGH) SCL clock high period 0.6 0.26 µs
tR SDA, SCL fall time 20 300 120 ns
tF SDA, SCL fall time 20 x
(VCC / 5.5 V)		 300 20 x
(VCC / 5.5 V)		 120 ns
tLPF Glitch suppression filter 50 50 ns
(1) The host and device have the same VCC value. Values are based on statistical analysis of samples tested during initial release.
(2) The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time.