SLYS045B June   2021  – July 2024 TMAG5273

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Temperature Sensor
    7. 5.7  Magnetic Characteristics For A1, B1, C1, D1
    8. 5.8  Magnetic Characteristics For A2, B2, C2, D2
    9. 5.9  Magnetic Temp Compensation Characteristics
    10. 5.10 I2C Interface Timing
    11. 5.11 Power up & Conversion Time
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Magnetic Flux Direction
      2. 6.3.2 Sensor Location
      3. 6.3.3 Interrupt Function
      4. 6.3.4 Device I2C Address
      5. 6.3.5 Magnetic Range Selection
      6. 6.3.6 Update Rate Settings
    4. 6.4 Device Functional Modes
      1. 6.4.1 Standby (Trigger) Mode
      2. 6.4.2 Sleep Mode
      3. 6.4.3 Wake-up and Sleep (W&S) Mode
      4. 6.4.4 Continuous Measure Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Interface
        1. 6.5.1.1 SCL
        2. 6.5.1.2 SDA
        3. 6.5.1.3 I2C Read/Write
          1. 6.5.1.3.1 Standard I2C Write
          2. 6.5.1.3.2 General Call Write
          3. 6.5.1.3.3 Standard 3-Byte I2C Read
          4. 6.5.1.3.4 1-Byte I2C Read Command for 16-Bit Data
          5. 6.5.1.3.5 1-Byte I2C Read Command for 8-Bit Data
          6. 6.5.1.3.6 I2C Read CRC
      2. 6.5.2 Data Definition
        1. 6.5.2.1 Magnetic Sensor Data
        2. 6.5.2.2 Temperature Sensor Data
        3. 6.5.2.3 Angle and Magnitude Data Definition
        4. 6.5.2.4 Magnetic Sensor Offset Correction
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Select the Sensitivity Option
      2. 7.1.2 Temperature Compensation for Magnets
      3. 7.1.3 Sensor Conversion
        1. 7.1.3.1 Continuous Conversion
        2. 7.1.3.2 Trigger Conversion
        3. 7.1.3.3 Pseudo-Simultaneous Sampling
      4. 7.1.4 Magnetic Limit Check
      5. 7.1.5 Error Calculation During Linear Measurement
      6. 7.1.6 Error Calculation During Angular Measurement
    2. 7.2 Typical Application
      1. 7.2.1 Magnetic Tamper Detection
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 I2C Address Expansion
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Angle Measurement
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
          1. 7.2.3.2.1 Gain Adjustment for Angle Measurement
        3. 7.2.3.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Register Maps
    1. 8.1 TMAG5273 Registers
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10 I2C Interface Timing

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I2C Interface Fast Mode Plus (VCC =2.3V to 3.6V)
fI2C_fmp I2C clock (SCL) frequency LOAD = 50pF
VCC = 2.3V to 3.6V		 1000 KHz
twhigh_fmp High time: SCL logic high time duration 350 ns
twlo_wfmp Low time: SCL logic low time duration 500 ns
tsu_cs_fmp SDA data setup time 50 ns
th_cs_fmp SDA data hold time 120 ns
ticr_fmp SDA, SCL input rise time 120 ns
ticf_fmp SDA, SCL input fall time 55 ns
th_ST_fmp Start condition hold time 0.1 µs
tsu_SR_fmp Repeated start condition setup time 0.1 µs
tsu_SP_fmp Stop condition setup time 0.1 µs
tw_SP_SR_fmp Bus free time between stop and start condition 0.2 µs
I2C Interface Fast Mode (VCC =1.7V to 3.6V)
fI2C I2C clock (SCL) frequency LOAD = 50pF
VCC = 1.7V to 3.6V		 400 KHz
twhigh High time: SCL logic high time duration 600 ns
twlow Low time: SCL logic low time duration 1300 ns
tsu_cs SDA data setup time 100 ns
th_cs SDA data hold time 0 ns
ticr SDA, SCL input rise time 300 ns
ticf SDA, SCL input fall time 300 ns
th_ST Start condition hold time 0.3 µs
tsu_SR Repeated start condition setup time 0.3 µs
tsu_SP Stop condition setup time 0.3 µs
tw_SP_SR Bus free time between stop and start condition 0.6 µs