SLLSF57A August 2022 – April 2024 TMDS1204
PRODUCTION DATA
The TMDS1204 supports adaptive equalization (AEQ) for HDMI 2.1 FRL. It does not support AEQ for HDMI 1.4 or 2.0. In HDMI 1.4 and HDMI 2.0 modes, TMDS1204 will use the sampled state of the EQ[1:0] pins or value programmed into the register. The AEQ is supported in some pin-strap modes as well as in I2C mode. In I2C mode, AEQ can be enabled by setting the AEQ_EN register. The TMDS1204 adaptation algorithm scans through available equalization settings searching for a setting for which the incoming high-speed signal is not over equalized.
The TMDS1204 will perform adaptive equalization when FRL link training begins. It will also re-adapt each time the data rate changes. The adaption will only occur during the TXFFE0 portion of FRL link training when LTP5, LTP6, LTP7, or LTP8 is being received. The TMDS1204 adaption will complete within tAEQ_DONE from the time FRL link training begins. If the sink requests additional TXFFE levels (TXFFE1, 2, or 3), then the TMDS1204 will keep its equalizer settings fixed at the value adapted during TXFFE0. If for some reason the FRL link training fails and transitions to legacy mode (HDMI 1.4 or HDMI 2.0), then the EQ [1:0] pins sample the EQ settings that the TMDS1204 switches to if in pin-strap mode or programmed into the register (if in I2C mode).
The TMDS1204 will keep OUT_D[2:0] and OUT_CLK disabled until after adaptation completes. After adaptation completes, the appropriate lanes will be enabled. In I2C mode, this behavior can be overridden by clearing the AEQ_TX_DELAY_EN field.
CTLEMAP_SEL pin level | ||||
---|---|---|---|---|
MODE pin level | 0 | R | F | 1 |
0 |
AEQ disabled |
AEQ disable |
AEQ disabled |
AEQ disabled |
R |
AEQ disabled |
AEQ disabled |
AEQ enabled |
AEQ enabled |
F |
I2C register |
I2C register |
I2C register |
I2C register |
1 |
AEQ disabled |
AEQ disabled |
AEQ enabled |
AEQ enabled |
The AEQ operates only on IN_D0 pins (pins 12 and 13). The EQ value determined by AEQ will be applied to the other FRL data lanes.