SLLSF57A August   2022  – April 2024 TMDS1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD and Latch-Up Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1  4-Level Inputs
      2. 7.2.2  I/O Voltage Level Selection
      3. 7.2.3  HPD_OUT
      4. 7.2.4  Lane Control
      5. 7.2.5  Swap
      6. 7.2.6  Linear and Limited Redriver
      7. 7.2.7  Main Link Inputs
      8. 7.2.8  Receiver Equalizer
      9. 7.2.9  CTLE Bypass
      10. 7.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 7.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 7.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 7.2.12 Input Signal Detect
        1. 7.2.12.1 SIGDET_OUT Indicator
      13. 7.2.13 Main Link Outputs
        1. 7.2.13.1 Transmitter Bias
        2. 7.2.13.2 Transmitter Impedance Control
        3. 7.2.13.3 TX Slew Rate Control
        4. 7.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 7.2.13.5 TX Swing Control
        6. 7.2.13.6 Fan-out Buffer
      14. 7.2.14 HDMI DDC Capacitance
      15. 7.2.15 DisplayPort
    3. 7.3 Device Functional Modes
      1. 7.3.1 MODE Control
        1. 7.3.1.1 I2C Mode (MODE = "F")
        2. 7.3.1.2 Pin Strap Modes
          1. 7.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 7.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ)
          3. 7.3.1.2.3 Pin-Strap HDMI 2.1 Function (Mode = "1"): Flexible Rx EQ
          4. 7.3.1.2.4 Pin-Strap HDMI 2.1 Function (Mode = "R"): Flexible Rx EQ and Fan-Out Buffer
      2. 7.3.2 DDC Snoop Feature
        1. 7.3.2.1 HDMI Type
        2. 7.3.2.2 HDMI 2.1 FRL Snoop
      3. 7.3.3 Low Power States
    4. 7.4 Programming
      1. 7.4.1 Pseudocode Examples
        1. 7.4.1.1 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
        2. 7.4.1.2 Sink Example
      2. 7.4.2 TMDS1204 I2C Address Options
      3. 7.4.3 I2C Target Behavior
    5. 7.5 Register Maps
      1. 7.5.1 TMDS1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Source-Side Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Pre-Channel (LAB)
        2. 8.2.2.2 Post-Channel (LCD)
        3. 8.2.2.3 Common Mode Choke
        4. 8.2.2.4 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Typical Sink-Side Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedures
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Supply Decoupling
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-82D7336E-A043-4FEA-B95F-C7946024F18B-low.gifFigure 4-1 RNQ Package, 40-Pin WQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
VCC 1 P 3.3V power supply
RCLKOUTp 2 O HDMI 1.4/2.0 clock differential positive output when not operating in HDMI 2.1 FRL mode with Fan-out buffer feature enabled. External AC coupling required. If not used, then this pin can be left unconnected.
RCLKOUTn 3 O HDMI 1.4/2.0 clock differential negative output when not operating in HDM I2.1 FRL mode with Fan-out buffer feature enabled. External AC coupling required. If not used, then this pin can be left unconnected.
CTLEMAP_SEL 4 I
4 Level (PU/PD)		 CTLE Map select. When TMDS1204 is configured in pin-strap mode, this pin selects the CTLE Map used. Table 7-8 provides more details. Also in pin-strap this pin will control whether or not AEQ is enabled. Table 7-9 provides more details. In I2C mode, CTLE Map and AEQ enable is determined by registers.
LINEAR_EN 5 I
4-Level (PU/PD)		 In pin-strap mode, selects whether TMDS1204 operates in linear or limited redriver mode. Table 7-5 provides more details.
VCC 6 P 3.3V power supply
EN 7 I
2-Level (PU)		 When low, TMDS1204 will be held in reset. The IN_D[2:0], IN_CLK, OUT_D[2:0] and OUT_CLK pins will be held in high impedance while EN is low. On rising edge of EN, device will sample four-level inputs and function based on the sampled state of the pins. This pin has a internal 250 k pull-up to VIO.
EQ1 8 I
4 Level (PU/PD)		 EQ1 Pin Setting when TMDS1204 is configured for pin strap mode; Works in conjunction with EQ0; Table 7-6 provides the settings. In I2C mode, EQ settings are controlled through registers.
IN_CLKn 9 I Clock differential negative input.
IN_CLKp 10 I Clock differential positive input.
HPD_OUT 11 O Hot plug detect output to source side. If not used, then this pin can be left floating.
IN_D0n 12 I Channel 0 differential negative input.
IN_D0p 13 I Channel 0 differential positive input.
VIO 14 P Voltage supply for I/Os. Table 7-2 provides more information.
IN_D1n 15 I Channel 1 differential negative input.
IN_D1p 16 I Channel 1 differential positive input.
MODE 17 I
4 Level (PU/PD)		 Mode control pin. Selects between pin-strap and I2C mode. For more information, refer to Section 7.3.1.
IN_D2n 18 I Channel 2 differential negative input.
IN_D2p 19 I Channel 2 differential positive input.
VCC 20 P 3.3V power supply.
SCL/CFG0 21 I I2C Clock/CFG0: when TMDS1204 is configured for I2C mode, this pin will function as the I2C clock. Otherwise, this pin will function as CFG0. Table 7-18 provides more details.
SDA/CFG1 22 I/O I2C Data / CFG1: When TMDS1204 is configured for I2C mode, this pin will function as the I2C clock. Otherwise, this pin will function as CFG1. Table 7-19 provides more details.
AC_EN 23 I
2-Level (PD)		 In pin-strap mode, selects whether high speed transmitters are externally AC or DC coupled.
0: DC-coupled
1: AC-coupled
LV_DDC_SCL 24 I/O Low voltage side DDC clock line. Internally pulled-up to VIO.
LV_DDC_SDA 25 I/O Low voltage side DDC data line. Internally pulled-up to VIO.
SIGDET_OUT 26 O SIGDET_OUT. Open drain output asserted low when signal is detected on IN_CLK or IN_D2 when HPD_IN is high. Otherwise signal is de-asserted. When used requires 10k or greater pull-up resistor.
DCGAIN 27 I
4 Level (PU/PD)		 DC Gain.
"0": −3dB
"R": −3dB
"F": 0dB
"1": +1dB
VCC 28 P 3.3V power supply
TXPRE 29 I
4 Level (PU/PD)		 TX pre-emphasis control: in pin-strap mode with limited enabled, this pin controls TX EQ. In pin-strap with linear and AEQ enabled, this pin will adjust the adapted value. Table 7-15 provides the available TXPRE settings when operating in pin strap mode. In I2C mode, Tx pre-emphasis is controlled through registers.
OUT_D2p 30 O TMDS data 2 differential positive output
OUT_D2n 31 O TMDS data 2 differential negative output
HPD_IN 32 I
2-Level (PD)		 Hot plug detect input from sink side. This pin has an internal pull-down resistor and is fail-safe.
OUT_D1p 33 O TMDS data 1 differential positive output
OUT_D1n 34 O TMDS data 1 differential negative output
ADDR/EQ0 35 I
4 Level (PU/PD)		 Address bit for I2C programming when TMDS1204 is configured for I2C mode. Table 7-22 provides more details.
EQ0 pin setting when TMDS1204 is configured for pin strap mode; works in conjunction with EQ1; Table 7-6 lists the settings. In I2C mode, EQ settings are controlled through registers.
OUT_D0p 36 O TMDS data 0 differential positive output
OUT_D0n 37 O TMDS data 0 differential negative output
TXSWG 38 I
4 Level (PU/PD)		 TX output swing control: 4 settings. This pin is only used in pin strap mode. Table 7-17 provides the available TX swing settings. In I2C mode, TX output swing is controlled through registers.
OUT_CLKp 39 O TMDS data clock differential positive output
OUT_CLKn 40 O TMDS data clock differential negative output
Thermal Pad — Thermal pad. Connect to a solid ground plane.
(1) I = input, O = output, P = power, G = ground