SLLSF57A August   2022  – April 2024 TMDS1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD and Latch-Up Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1  4-Level Inputs
      2. 7.2.2  I/O Voltage Level Selection
      3. 7.2.3  HPD_OUT
      4. 7.2.4  Lane Control
      5. 7.2.5  Swap
      6. 7.2.6  Linear and Limited Redriver
      7. 7.2.7  Main Link Inputs
      8. 7.2.8  Receiver Equalizer
      9. 7.2.9  CTLE Bypass
      10. 7.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 7.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 7.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 7.2.12 Input Signal Detect
        1. 7.2.12.1 SIGDET_OUT Indicator
      13. 7.2.13 Main Link Outputs
        1. 7.2.13.1 Transmitter Bias
        2. 7.2.13.2 Transmitter Impedance Control
        3. 7.2.13.3 TX Slew Rate Control
        4. 7.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 7.2.13.5 TX Swing Control
        6. 7.2.13.6 Fan-out Buffer
      14. 7.2.14 HDMI DDC Capacitance
      15. 7.2.15 DisplayPort
    3. 7.3 Device Functional Modes
      1. 7.3.1 MODE Control
        1. 7.3.1.1 I2C Mode (MODE = "F")
        2. 7.3.1.2 Pin Strap Modes
          1. 7.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 7.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ)
          3. 7.3.1.2.3 Pin-Strap HDMI 2.1 Function (Mode = "1"): Flexible Rx EQ
          4. 7.3.1.2.4 Pin-Strap HDMI 2.1 Function (Mode = "R"): Flexible Rx EQ and Fan-Out Buffer
      2. 7.3.2 DDC Snoop Feature
        1. 7.3.2.1 HDMI Type
        2. 7.3.2.2 HDMI 2.1 FRL Snoop
      3. 7.3.3 Low Power States
    4. 7.4 Programming
      1. 7.4.1 Pseudocode Examples
        1. 7.4.1.1 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
        2. 7.4.1.2 Sink Example
      2. 7.4.2 TMDS1204 I2C Address Options
      3. 7.4.3 I2C Target Behavior
    5. 7.5 Register Maps
      1. 7.5.1 TMDS1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Source-Side Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Pre-Channel (LAB)
        2. 8.2.2.2 Post-Channel (LCD)
        3. 8.2.2.3 Common Mode Choke
        4. 8.2.2.4 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Typical Sink-Side Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedures
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Supply Decoupling
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.13.2 Transmitter Impedance Control

HDMI 2.0 standards require a source termination impedance approximately 100Ω for data rates > 3.4Gbps. HDMI 1.4b requires no source termination but has a provision for termination for higher data rates greater than 1.65Gbps. Enabling this termination is optional. Table 7-13 lists how the TMDS1204 terminations are controlled automatically when in pin strap mode. Depending on the MODE pin, the CFG0 pin can be used to select the HDMI 1.4 termination between open and 300Ω.

The TMDS1204 supports automatic selection between open and 300Ω termination when operating in HDMI 1.4. In pin-strap mode with CTL0 low, the TMDS1204 will enable open termination when HDMI clock frequency is less than fHDMI14_open and will enable 300Ω termination when HDMI clock frequency is greater than fHDMI14_300. TXTERM_AUTO_HDMI14 register controls this feature in I2C mode.

In I2C mode, termination is controlled through the registers as provided in Table 7-12.

Table 7-12 Source Termination Control in I2C mode
TX_AC_EN Register TERM Register TXTERM_AUTO_HDMI14 Register Source Termination
0 00 X None
0 01 X Parallel ≅ 300Ω across P and N
0 10 X Automatic. HDMI 2.0 or HDM 2.1. parallel ≅ 100Ω across P and N
0 10 1 Automatic. HDMI 1.4. parallel ≅ 300Ω across P and N
0 10 0 Automatic. HDMI 1.4. No termination if HDMI clock frequency is ≤ fHDMI14_open.
0 10 0 Automatic. HDMI 1.4. Parallel ≅ 300Ω across P and N termination if HDMI clock frequency is ≥ fHDMI14_300.
0 11 X Parallel ≅ 100Ω across P and N
1 00 X ≅ 150Ω to supply (VCC) on both P and N
1 01 X ≅ 150Ω to supply (VCC) on both P and N
1 10 X Automatic. ≅ 150Ω to supply (VCC) on both P and N for HDMI 1.4. Otherwise ≅ 50Ω to supply (VCC) on both P and N.
1 11 X ≅ 50Ω to supply (VCC) on both P and N
Table 7-13 Automatic Source Termination Control in Pin-Strap Mode
HDMI ModeAC_EN pinSource Termination
HDMI 1.40None or parallel ≅ 300Ω across P and N depending on state of SCL/CFG0 pin
HDMI 2.00Parallel ≅ 100Ω across P and N
HDMI 1.41≅ 150Ω to supply (VCC) on both P and N
HDMI 2.01≅ 50Ω to supply (VCC) on both P and N