SLLSEN7E October   2015  – September 2017 TMDS171

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reset Implementation
      2. 8.3.2  Operation Timing
      3. 8.3.3  Swap and Polarity Working (Retimer Mode Only)
      4. 8.3.4  TMDS Inputs
      5. 8.3.5  TMDS Inputs Debug Tools
      6. 8.3.6  Receiver Equalizer
      7. 8.3.7  Input Signal Detect Block
      8. 8.3.8  Audio Return Channel
      9. 8.3.9  Transmitter Impedance Control
      10. 8.3.10 TMDS Outputs
      11. 8.3.11 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Functional Description
      4. 8.4.4 Mode Selection Functional Description
    5. 8.5 Register Maps
      1. 8.5.1  Local I2C Overview
        1. 8.5.1.1 BIT Access Tag Conventions
      2. 8.5.2  CSR Bit Field Definitions, DEVICE_ID (offset: 00000000 ≈ 00000111) (reset:00h ≈ 07h)
      3. 8.5.3  CSR Bit Field Definitions, REV _ID (offset: 00001000) (reset: 01h)
      4. 8.5.4  CSR BIT Field Definitions - Misc Control (offset: 00001001) (reset: 02h)
      5. 8.5.5  CSR BIT Field Definitions - Misc Control (offset: 00001010) (reset: B1h)
      6. 8.5.6  CSR BIT Field Definitions - Misc Control (offset: 00001011) (reset: 00h)
      7. 8.5.7  CSR BIT Field Definitions - Misc Control (offset: 00001100) (reset: 00h)
      8. 8.5.8  CSR BIT Field Definitions - Equalization Control Register (offset: 00001101) (reset: 01h)
      9. 8.5.9  CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00001110) (reset: 00h)
      10. 8.5.10 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00001111) (reset: 00h)
      11. 8.5.11 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010000) (reset: 00h)
      12. 8.5.12 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010001) (reset: 00h)
      13. 8.5.13 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010010) (reset: 00h)
      14. 8.5.14 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010011) (reset: 00h)
      15. 8.5.15 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010100) (reset: 00h)
      16. 8.5.16 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010101) (reset: 00h)
      17. 8.5.17 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010110) (reset: 00h)
      18. 8.5.18 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010111) (reset: 00h)
      19. 8.5.19 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011000) (reset: 00h)
      20. 8.5.20 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011001) (reset: 00h)
      21. 8.5.21 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011010) (reset: 00h)
      22. 8.5.22 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011011) (reset: 00h)
      23. 8.5.23 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011100) (reset: 00h)
      24. 8.5.24 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011101) (reset: 00h)
      25. 8.5.25 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011110) (reset: 00h)
      26. 8.5.26 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011111) (reset: 00h)
      27. 8.5.27 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00100000) (reset: 00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Chain Showing DDC Connections
      2. 9.1.2 DDC Pull Up Resistors
    2. 9.2 Source Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Sink Side Application
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGZ (QFN) Package
48 Pins
Top View
TMDS171 TMDS171I po_sllsen7.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
VCC 13, 43 P 3.3 V Power Supply
VDD 14, 23, 24, 37, 48 P 1.2 V Power Supply
GND 7, 19, 41, 30 G Ground
Thermal Pad G Ground
MAIN LINK INPUT PINS (FAIL SAFE)
IN_D2p/n 2, 3 I Channel 2 Differential Input
IN_D1p/n 5, 6 I Channel 1 Differential Input
IN_D0p/n 8, 9 I Channel 0 Differential Input
IN_CLKp/n 11, 12 I Clock Differential Input
MAIN LINK OUTPUT PINS (FAIL SAFE)
OUT_D2n/p 34, 35 O TMDS Data 2 Differential Output
OUT_D1n/p 31, 32 O TMDS Data 1 Differential Output
OUT_D0n/p 28, 29 O TMDS Data 0 Differential Output
OUT_CLKn/p 25, 26 O TMDS Clock Differential Output
HOT PLUG DETECT PINS
HPD_SRC 4 O Hot Plug Detect Output to source side
HPD_SNK 33 I Hot Plug Detect Input from sink side
AUDIO RETURN CHANNEL and DDC PINS
SPDIF_IN 45 I SPDIF signal input
ARC_OUT 44 O Audio return channel output
SDA_SRC 47 I/O Source Side TMDS Port Bidirectional DDC Data line
SCL_SRC 46 I/O Source Side TMDS Port Bidirectional DDC Clock line
SDA_SNK, 39 I/O Sink Side TMDS Port Bidirectional DDC Data Line
SCL_SNK 38 I/O Sink Side TMDS Port Bidirectional DDC Clock Line
CONTROL PINS(2)
OE 42 I Operation Enable/Reset Pin
OE = L: Power Down Mode
OE = H: Normal Operation
Internal weak pull up: Resets device when transitions from H to L
SIG_EN 17 I Signal detector circuit enable
SIG_EN = L: Signal Detect Circuit Disabled: Term resistors always connected (Default)
SIG_EN = H: Signal Detect Circuit Enabled: When no valid clock device enters Standby Mode.
Internal weak pull down
PRE_SEL 20 I
3-Level		 De-emphasis Control when I2C_EN/PIN = Low.
PRE_SEL = L: -2 dB
PRE_SEL = No Connect: 0 dB
PRE_SEL = H: Reserved
When I2C_EN/PIN = High; De-emphasis is controlled through I2C
EQ_SEL/A0 21 I Input Receive Equalization pin strap when I2C_EN/PIN = Low
EQ_SEL = L: Fixed EQ at 7.5 dB
EQ_SEL = No Connect: Adaptive EQ
EQ_SEL = H: Fixed at 14 dB
When I2C_EN/PIN = High Address Bit 1
Note: 3 level for pin strap programming but 2 level when I2C address
I2C_EN/PIN 10 I I2C_EN/PIN = High; Puts Device into I2C Control Mode
I2C_EN/PIN = Low; Puts Device into Pin Strap Mode
SCL_CTL 15 I/O I2C Clock Signal when I2C_EN/PIN = High.
Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be changed by I2C
SDA_CTL 16 I/O I2C Data Signal when I2C_EN/PIN = High
Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be changed by I2C
VSadj 22 I TMDS Output Voltage Swing Control; Nominal 7.06 kΩ Resistor to GND
A1 27 I High address bit 2 for I2C programming
Weak internal pull down.
Note: When I2C_EN/PIN = Low for Pin Strapping Mode leave this pin as No connect
TX_TERM_CTL 36 I
3-Level		 Transmit Termination Control
TX_TERM_CTL = H: No transmit Termination
TX_TERM_CTL = L: Reserved
TX_TERM_CTL = No Connect: Automatically selects the termination impedance
2 Gbps > DR ≤ 3.4 Gbps – 150 - 300 Ω differential near end termination
DR < 2 Gbps – no termination
Note: If left floating; the device will be in Automatic Select Mode. DR stands for Data Rate
SWAP/POL 1 I
3-Level		 Receive Polarity Swap and Receive Lane Swap control pin
SWAP/POL = H: Receive Lanes Polarity Swap (Retimer Mode Only)
SWAP/POL = L: Receive Lanes (Retimer and Redriver Mode)
Swap SWAP/POL = No Connect, Normal Operation
NC 18, 40 – No connect
(1) (1) G = Ground, I = Input, O = Output, P = Power
(2) (H) Logic High (Pin strapped to VCC through 65 kΩ resistor); (L) Logic Low (Pin strapped to GND through 65 kΩ resistor); (Mid-Level = No connect)