SLLSEN7E October   2015  – September 2017 TMDS171

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reset Implementation
      2. 8.3.2  Operation Timing
      3. 8.3.3  Swap and Polarity Working (Retimer Mode Only)
      4. 8.3.4  TMDS Inputs
      5. 8.3.5  TMDS Inputs Debug Tools
      6. 8.3.6  Receiver Equalizer
      7. 8.3.7  Input Signal Detect Block
      8. 8.3.8  Audio Return Channel
      9. 8.3.9  Transmitter Impedance Control
      10. 8.3.10 TMDS Outputs
      11. 8.3.11 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Functional Description
      4. 8.4.4 Mode Selection Functional Description
    5. 8.5 Register Maps
      1. 8.5.1  Local I2C Overview
        1. 8.5.1.1 BIT Access Tag Conventions
      2. 8.5.2  CSR Bit Field Definitions, DEVICE_ID (offset: 00000000 ≈ 00000111) (reset:00h ≈ 07h)
      3. 8.5.3  CSR Bit Field Definitions, REV _ID (offset: 00001000) (reset: 01h)
      4. 8.5.4  CSR BIT Field Definitions - Misc Control (offset: 00001001) (reset: 02h)
      5. 8.5.5  CSR BIT Field Definitions - Misc Control (offset: 00001010) (reset: B1h)
      6. 8.5.6  CSR BIT Field Definitions - Misc Control (offset: 00001011) (reset: 00h)
      7. 8.5.7  CSR BIT Field Definitions - Misc Control (offset: 00001100) (reset: 00h)
      8. 8.5.8  CSR BIT Field Definitions - Equalization Control Register (offset: 00001101) (reset: 01h)
      9. 8.5.9  CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00001110) (reset: 00h)
      10. 8.5.10 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00001111) (reset: 00h)
      11. 8.5.11 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010000) (reset: 00h)
      12. 8.5.12 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010001) (reset: 00h)
      13. 8.5.13 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010010) (reset: 00h)
      14. 8.5.14 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010011) (reset: 00h)
      15. 8.5.15 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010100) (reset: 00h)
      16. 8.5.16 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010101) (reset: 00h)
      17. 8.5.17 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010110) (reset: 00h)
      18. 8.5.18 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010111) (reset: 00h)
      19. 8.5.19 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011000) (reset: 00h)
      20. 8.5.20 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011001) (reset: 00h)
      21. 8.5.21 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011010) (reset: 00h)
      22. 8.5.22 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011011) (reset: 00h)
      23. 8.5.23 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011100) (reset: 00h)
      24. 8.5.24 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011101) (reset: 00h)
      25. 8.5.25 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011110) (reset: 00h)
      26. 8.5.26 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011111) (reset: 00h)
      27. 8.5.27 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00100000) (reset: 00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Chain Showing DDC Connections
      2. 9.1.2 DDC Pull Up Resistors
    2. 9.2 Source Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Sink Side Application
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)(3)
MIN MAX UNIT
Supply Voltage Range VCC –0.3 4 V
VDD –0.3 1.4
Voltage Range Main Link Input Differential Voltage (IN_Dx, IN_CLKx); IIN = 15mA VCC - 0.75 V VCC + 0.3 V
TMDS Outpus ( OUT_Dx) –0.3 4
HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1, PRE_SEL, EQ_SEL/A0, I2C_EN/PIN, SIG_EN, TX_TERM_CTL, –0.3 4
HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC, SCL_SRC –0.3 6
Input Current IIN Main Link Input Differential Voltage (IN_Dx, IN_CLKx); 15 mA
Continuous power dissipation See Thermal Information
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply Voltage Nominal Value 3.3 V 3.135 3.3 3.465 V
VDD Supply Voltage Nominial Value 1.2 V 1.1 1.2 1.27 V
TSTG Storage temperature –65 150 °C
TCASE Case temperature 92.7 °C
TA Operating free-air temperature (TMDS171) 0 85 °C
Operating free-air temperature (TMDS171I) –40 85 °C
MAIN LINK DIFFERENTIAL PINS
VID(PP) Peak-to-peak input differential voltage 75 1560 mVpp
VIC Input Common Mode Voltage VCC – 0.4 VCC + 0.1 V
dR Data rate 0.25 3.4 Gbps
R(VSADJ) TMDS compliant swing voltage bias resistor 1% 7.06 KΩ
CONTROL PINS
VI(DC) DC Input Voltage –0.3 3.6 V
VIL(1) Low-level input voltage OE 0.8 V
Low-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only(1) 0.3 V
VIM(1) Mid-Level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only(1) 1 1.2 1.4 V
VIH(1) High-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL, OE(2) pins only(1) 2.6 V
VOL Low-level output voltage 0.4 V
VOH High-level output voltage 2.4 V
IIH High level input current 30 30 µA
IIL Low level input current –25 25 µA
IOS Short circuit output current –50 50 mA
IOZ High impedance output current 10 µA
R(OEPU) Pull up resistance on OE pin 150 250 KΩ
(1) These values are based upon a microcontroller driving the control pins. The pull up/down/floating resistor configuration will set control pins properly which will have a different value than shown due to internal biasing.
(2) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup resistor will set OE pin properly, but may have a different value than shown due to internal biasing.

6.4 Thermal Information

THERMAL METRIC(1) RGZ (QFN) UNIT
48 PINS
RθJA Junction-to-ambient thermal resistance 31.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.2
RθJB Junction-to-board thermal resistance 8.1
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 8.1
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at 3.3 VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply
P(D1)(1)(2) Device power Dissipation (Retimer Operation) OE = H, VCC = 3.3 V / 3.465 V, VDD = 1.2 V / 1.27 V
IN_Dx: VID_PP = 1200 mV, I2C_EN/PIN = L, PRE_SEL= H, EQ_CTL= H, SDA_CTL/CLK_CTL = 0 V
3.4 Gbps TMDS pattern, VI = 3.3 V; VSADJ = 7.06 kΩ 		675 875 mW
P(D2)(1)(2) Device power Dissipation (Redriver Operation) 400 600 mW
P(SD1)(1)(2)(3) Device power in Standby OE = H, VCC = 3.3 V / 3.465 V
VDD = 1.2 V / 1.27 V , HPD = H,
No Valid input Signal		 50 100 mW
P(SD2)(1)(2)(3) Device power in PowerDown OE = L, VCC = 3.3 V / 3.465 V
VDD = 1.2 V / 1.27 V		 10 30 mW
ICC1(1)(2) VCC Supply current (TMDS 3.4 Gpbs Retimer Mode) OE = H, VCC = 3.3 V / 3.465 V
VDD = 1.2 V / 1.27 V
IN_Dx: VID_PP = 1200 mV,
3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H 		80 140 mA
IDD1(1)(2) VDD Supply current (TMDS 3.4 Gpbs Retimer Mode) 286 325 mA
ICC2(1)(2) VCC Supply current (TMDS 3.4 Gpbs Redriver Mode) OE = H, VCC = 3.3 V / 3.465 V
VDD = 1.2 V / 1.27 V
IN_Dx: VID_PP = 1200 mV,
3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H, SDA_CTL/CLK_CTL = 0V, SLEW_CTL = H		 51 mA
IDD2(1)(2) VDD Supply current (TMDS 3.4 Gpbs Redriver Mode) 188 mA
I(SD1)(3) Standby current OE = H, VCC = 3.3 V / 3.465 V
VDD = 1.2 V / 1.27 V
HPD = H: No valid signal on IN_CLK		 3.3V Rail(1) 6 15 mA
1.2V Rail 40 50
I(SD2)(3) PowerDown current OE = L, VCC = 3.3 V / 3.465 V
VDD = 1.2 V / 1.27 V		 3.3V Rail(1) 2 5 mA
1.2V Rail 3.5 15
TMDS Differential Input
D(R_RX_DATA) TMDS data lanes data rate 0.25 3.4 Gbps
D(R_RX_CLK) TMDS clock lanes clock rate 25 340 MHz
tRX_DUTY Input clock duty circle 40% 50% 60%
tCLK_JIT Input clock jitter tolerance 0.3 Tbit
tDATA_JIT Input data jitter tolerance Test the TTP2 See Figure 11 150 ps
tRX_INTRA Input intra-pair skew tolerance Test at TTP2 when DR = 1.6 Gbps See Figure 11 112 ps
tRX_INTER Input inter-pair skew tolerance 1.8 ns
EQH(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0=H; Fixed EQ gain, test at 3.4 Gbps 14 dB
EQL(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0=L; Fixed EQ gain, test at 3.4 Gbps 7.5
EQZ(D) Adaptive EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0=NC; adaptive EQ 2 14
EQ(C) EQ gain for clock lane IN_CLKn/p EQ_SEL/A0=H,LNC 0
R(INT) Input differential termination impedance 90 100 115 Ω
TMDS Differential Output
VOH Single-ended high level output voltage PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ VCC - 10mV VCC + 10mV V
PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97 Gbps; VSadj = 7.06 kΩ VCC - 200mV VCC + 10mV
VOL Single-ended low level output voltage No Pre-emphasis, Load is 50 Ω pull ups to 3.135 V and 3.465 V PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ VCC - 600mV VCC - 400mV
PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97 Gbps; VSadj = 7.06 kΩ VCC - 700mV VCC - 400mV
V(SWING_DA) Single-ended output voltage swing on data lane PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC;
DR = ≤ 3.4 Gbps; VSadj = 7.06 kΩ		 400 500 600 mV
V(SWING_CLK) Single-ended output voltage swing on clock lane PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC;
DR = ≤ 3.4 Gbps; VSadj = 7.06 kΩ		 400 500 600
ΔV(SWING) Change in single-end output voltage swing per 100Ω ΔVSadj 20
ΔVOCM(SS) Change in steady state output common mode voltage between logic levels –5 5
VOD(PP) Initial output differential voltage before steady state when pre-emphasis or de-emphasis is implemented VSadj = 7.06 kΩ; PRE_SEL = NC, See Figure 8 800 1200
VOD(SS) Steady state output differential voltage VSadj = 7.06 kΩ; PRE_SEL = L, See Figure 9 600 1075
IOS Short circuit current limit Main link output shorted to GND 50 mA
ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; TMDS Outputs pulled to 3.3V through 50 Ω resistor 45 µA
R(TERM) Source Termination resistance 150 300 Ω
DDC and I2C
VI-DC SCL/SDA_SNK, SCL/SDA_SRC DC input voltage –0.3 5.5 V
SCL/SDA_CTL, DC input voltage –0.3 3.6 V
VIL SCL/SDA_SNK, SCL/SDA_SRC Low level input voltage 0.3 x VCC V
SCL/SDA_CTL Low level input voltage 0.3 x VCC V
VIH SCL/SDA_SNK, SCL/SDA_SRC high level input voltage 3 V
SCL/SDA_CTL high level input voltage 0.7 x VCC V
VOL SCL/SDA_CTL, SCL/SDA_SRC low level output voltage IO = 3 mA and VCC > 2 V 0.4 V
IO = 3 mA and VCC < 2 V 0.2 x VCC V
fSCL SCL clock frequency fast I2C mode for local I2C control 400 kHz
Cbus Total capacitive load for each bus line (DDC and local I2C pins) 400 pF
HPD
VIH High-level input voltage HPD_SNK 2.1 V
VIL Low-level input voltage HPD_SNK 0.8
VOH High-level output voltage IOH = -500 µA; HPD_SRC 2.4 3.6
VOL Low-level output voltage IOL = -500 µA; HPD_SRC 0 0.1
ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; HPD_SNK = 5 V 40
IH(HPD) High level input current Device powered; VIH = 5 V; IH(HPD) includes Rpd(HPD) resistor current 40 µA
Device powered; VIL = 0.8 V; IH(HPD) includes Rpd(HPD) resistor current 30
Rpd(HPD) HPD input termination to GND; VCC < 0 V 150 190 220 kΩ
SPDIF and ARC
V(EL) Operating DC voltage for single mode ARC output Test at ARC_OUT, see Figure 19 0 5 V
VIN(DC) Operating DC voltage for SPDIF input 0.05 V
V(SP_SW) Signal amplitude of SPDIF input 0.2 0.5 0.6 V
V(ElSWING) Signal amplitude on the ARC output Test at ARC_OUT, 75 Ω external termination resistor, see Figure 19 0.4 0.5 0.6 V
CLK(ARC) Signal frequency on ARC Test at ARC_OUT, see Figure 19 3.687 5.645±0.1% 13.517 MHz
Duty Cycle Output Clock Duty cycle 45% 50% 55%
Data Rate SPDIF Input DR 7.373 11.29 27.034 Mbps
tEDGE The rise/fall time for ARC output From 10% to 90% voltage level, see Figure 19 0.4 UI
R(IN_SPDIF) The Input Termination resistance for SPDIF 75 Ω
R(EST) Single mode Output Termination resistance 0.1 MHz to 128 times the maximum frame rate 36 55 75 Ω
(1) ICC is a direct result of the source design as the TMDS171 integrated receive termination resistor accounts for 85 mA to 100 mA.
(2) IDD is impacted by ARC usage. Connecting a 500 KΩ resistor to GND at SPDIF reduces the value by more than 20 mA.
(3) The measurements were made with no active source connected.

6.6 Switching Characteristics

The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TMDS Redriver Mode
DR Data rate (Redriver mode) 250 3400 Mbps
tPLH Propagation delay time (low to high) 250 600 ps
tPHL Propagation delay time (high to low) 250 800
tT1 Transition time (rise and fall time); measured at 20% and 80% levels for Data Lanes. TX_TERM_CTL=L; PRE_SEL=NC; Data Rate 3.4 Gbps; Clock 340 MHz 75
tSK1(T) Intra-pair output skew TX_TERM_CTL=NC; PRE_SEL=NC; 40
tSK2(T) Inter-pair output skew TX_TERM_CTL=NC; PRE_SEL=NC; 100
tJITD1 Total output data jitter DR = 750 Mbps, PRE_SEL = NC, EQ_SEL/A0 = NC. See Figure 5 at TTP3 0.2 Tbit
tJITC1 Total output clock jitter 0.25
TMDS Retimer Mode
DR Data rate (retimer mod ) 1.2 3.4 Gbps
d(XVR) Automatic redriver to Retimer Cross-Over Measured with input signal applied from 0 to 200 mVPP 0.75 1.00 1.25 Gbps
f(CROSSOVER) Crossover frequency hysteresis 250 MHz
PLL(BW) Data Retimer PLL bandwidth Default loop bandwidth setting 0.4 1 MHz
tACQ Input Clock Frequency Detection and Retimer Acquisition Time 180 µs
IJT1 Input Clock Jitter Tolerance Tested when data rate > 1.0 Gbps 0.3 Tbit
tT1 Transition time (rise and fall time); measured at 20% and 80% levels for Data Lanes. TMDS 75 ps
tDCD OUT_CLK ± duty cycle 40% 50% 60%
tSK_INTER Inter-pair output skew Default setting for internal inter-pair skew adjust, PRE_SEL = NC; TX_TERM_CTL = NC, DR ≤ 3.4 Gbps; See Figure 6 0.2 Tch
tSK_INTRA Intra-pair output skew Default setting for internal intra-pair skew adjust, PRE_SEL = NC; TX_TERM_CTL = NC, DR ≤ 3.4 Gbps; See Figure 6 0.15 Tbit
tJITC2 Total output clock jitter CLK Rate ≤ 340 MHz 0.25 Tbit
tJITD2 Total output data jitter DR ≤ 3.4 Gbps; See Figure 11 0.2 Tbit
HPD
tPD(HPD) Propagation delay from HPD_SNK to HPD_SRC; rising edge and falling edge(1) see Figure 13; not valid during switching time 40 120 ns
tT(HPD) HPD logical disconnected timeout see Figure 14 2 ms
DDC and I2C
tr Rise time of both SDA and SCL signals VCC = 3.3 V 300 ns
tf Fall time of both SDA and SCL signals 300
tHIGH Pulse duration, SCL high 0.6 µs
tLOW Pulse duration, SCL low 1.3
tSU1 Setup time, SDA to SCL 100 ns
tST,STA Setup time, SCL to start condition 0.6 µs
tHD,STA Hold time, start condition to SCL 0.6
tST,STO Setup time, SCL to stop condition 0.6
t(BUF) Bus free time between stop and start condition 1.3
tPLH1 Propagation delay time, low-to-high-level output Source to Sink:100 kbps pattern;
Cb(Sink) = 400 pF(2); see Figure 17		 360 ns
tPHL1 Propagation delay time, high-to-low-level output 230
tPLH2 Propagation delay time, low-to-high-level output Sink to Source: 100 kbps pattern;
Cb(Source) = 100 pF(2); see Figure 18		 250
tPHL2 Propagation delay time, high-to-low-level output 200
(1) The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD
(2) Cb = total capacitance of one bus line in pF.

6.7 Typical Characteristics

TMDS171 TMDS171I D001_SLLSEN7.gif
Figure 1. Current vs Data Rate Redriver Mode
TMDS171 TMDS171I D003_SLLSEL2.gif
Figure 3. VOD vs VSadj
TMDS171 TMDS171I D002_SLLSEN7.gif
Figure 2. Current vs Data Rate Retimer Mode