SBOS564B November 2011 – December 2018 TMP104
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Figure 8 shows the internal register structure of the TMP104. Communications between the registers are transferred through the interface in LSB-first order. The 8-bit Command Register, as shown in Table 3, is used to determine the type of instruction being addressed. These eight bits could either interpret a global instruction or an individual instruction, which is determined by the value of P7. When P7 = 0, the command byte interprets an individual instruction; when P7 = 1, the command byte interprets a global instruction.
P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
---|---|---|---|---|---|---|---|
GLB | IN3/ID3 | IN2/ID2 | IN1/ID1 | IN0/ID0 | P1 | P0 | R/W |