SBOS564B November   2011  – December 2018 TMP104

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Device Images
      1.      Typical Application
  4. 4Revision History
  5. 5Pin Configuration and Functions
    1.     Pin Functions
  6. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Timeout Function
      2. 7.2.2 Noise
      3. 7.2.3 SMAART Wire™ Interface Timing Specifications
    3. 7.3 Programming
      1. 7.3.1 Communication Protocol
      2. 7.3.2 Command Register
      3. 7.3.3 Global Initialization and Address Assignment Sequence
      4. 7.3.4 Global Read and Write
      5. 7.3.5 Global Clear Interrupt
      6. 7.3.6 Global Software Reset
      7. 7.3.7 Individual Read and Write
    4. 7.4 Register Maps
      1. 7.4.1 Temperature Register
      2. 7.4.2 Configuration Register
        1. 7.4.2.1 Temperature Watchdog Function (FH, FL)
        2. 7.4.2.2 Conversion Rate (CR1, CR0)
        3. 7.4.2.3 Conversion Modes
          1. 7.4.2.3.1 Shutdown Mode (M1 = 0, M0 = 0)
          2. 7.4.2.3.2 One-Shot Mode (M1 = 0, M0 = 1)
          3. 7.4.2.3.3 Continuous Conversion Mode (M1 = 1)
        4. 7.4.2.4 Interrupt Functionality (INT_EN)
      3. 7.4.3 Temperature Limit Registers
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2.4 Interrupt Functionality (INT_EN)

The TMP104 interrupts the host by disconnecting the bus and issuing an interrupt request by holding the bus low if all of these conditions are met, as shown in Figure 15:

  • INT_EN in the Configuration Register is set to '1';
  • The temperature result is higher than the value in the THIGH register or lower than the value in the TLOW register (as indicated by a '1' in either FL or FH);
  • The bus is logic high and idle for more than 28 ms.
TMP104 ai_bus_stat_daisy_read_second_bos564.gifFigure 15. TMP104 Daisy-Chain:
Bus Status During an Interrupt Request (Logic Low) From Second Device

The interrupt on the bus is latched regardless of the status of LC. Writing a '1' to INT_EN automatically sets the LC bit. The TMP104 holds the bus low until one of the following events happen:

  • Global Interrupt Clear command received;
  • Global Software Reset command received;
  • A power-on reset event occurs.

Each of these events clears INT_EN; the TMP104 does not issue future interrupts until the host writes '1' to bit D7 in the Configuration Register to re-enable future interrupts.

In a system with enabled interrupts, it is possible for a TMP104 on the bus to issue an interrupt at the same time that the host starts a communication sequence. To avoid this scenario, it is recommended that the host should check the status on the receiving side of the bus after transmitting the calibration byte. If it is '1', then the host can continue with the communication. If it is '0', one of the TMP104 devices on the bus is issuing an alert and the host must transmit a Global Interrupt Clear command.