SBOS564B November 2011 – December 2018 TMP104
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Figure 6 shows the key timing and jitter considerations for the SMAART wire interface. Table 1 lists the timing specifications for ensured, reliable operation. During a transaction, the baud rate must remain within ±1% of its initialization byte value; however, the baud rate can change from transaction to transaction. There is an allowed delay between each byte transfer of less than 28 ms, which is the bus inactivity timeout check for the TMP104 SMAART wire interface.
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
Baud | 4.8 k | 114 k | Bits/s | |
tR | Clock/data rise time | 0.5 | %Baud | |
tF | Clock/data fall time | 0.5 | %Baud | |
Jitter | ±1 | %Baud |