SNIS227C May   2021  – June 2022 TMP126-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1 Temperature Limits
      2. 8.3.2 Slew Rate Warning
      3. 8.3.3 Cyclic Redundancy Check (CRC)
      4. 8.3.4 NIST Traceability
      5. 8.3.5 Fast Measurement Intervals With No Self-Heating Concerns
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conversion Mode
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 One-Shot Mode
      4. 8.4.4 Interrupt and Comparator Mode
        1. 8.4.4.1 Interrupt Mode
        2. 8.4.4.2 Comparator Mode
    5. 8.5 Programming
      1. 8.5.1 Temperature Data Format
      2. 8.5.2 Serial Bus Interface
        1. 8.5.2.1 Command Word Structure
          1. 8.5.2.1.1 Don't Care
          2. 8.5.2.1.2 CRC Enable
          3. 8.5.2.1.3 CRC Data Block Length
          4. 8.5.2.1.4 Auto Increment
          5. 8.5.2.1.5 Read/Write
          6. 8.5.2.1.6 Sub-Address
        2. 8.5.2.2 Communication
        3. 8.5.2.3 Write Operations
        4. 8.5.2.4 Read Operations
        5. 8.5.2.5 Cyclic Redundancy Check (CRC)
          1. 8.5.2.5.1 Cyclic Redundancy Check Implementation
    6. 8.6 Register Map
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.2.5 Cyclic Redundancy Check (CRC)

The TMP126-Q1 has an optional CRC feature to determine the integrity of the data that has been transmitted across the SPI communication interface. The CRC for the TMP126-Q1 is enabled by setting the CRC bit in the command word to 1. When enabled, the TMP126-Q1 will append a 16-bit CRC checksum to the end the data block for read transactions. The controller can then compare this checksum to their own calculation and determine if the transaction was valid. During a write transaction, the host will append the 16-bit CRC checksum. The TMP126-Q1 will compare this to its own checksum. If there is a mismatch, the TMP126 will discard the write transaction and set a CRC fault ALERT to indicate to the host that the transaction failed. The host will need to send the register settings again to correctly program the TMP126-Q1. Reading the Alert_Status register will clear the CRC_Fault bit and de-assert the ALERT pin.

An overview of a CRC enabled write transaction is shown below with a data block length of 2.

Figure 8-15 CRC Enabled Write

An overview of a CRC enabled read transaction is shown below with a data block length of 2.

Figure 8-16 CRC Enabled Read