SNIS227C May   2021  – June 2022 TMP126-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1 Temperature Limits
      2. 8.3.2 Slew Rate Warning
      3. 8.3.3 Cyclic Redundancy Check (CRC)
      4. 8.3.4 NIST Traceability
      5. 8.3.5 Fast Measurement Intervals With No Self-Heating Concerns
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conversion Mode
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 One-Shot Mode
      4. 8.4.4 Interrupt and Comparator Mode
        1. 8.4.4.1 Interrupt Mode
        2. 8.4.4.2 Comparator Mode
    5. 8.5 Programming
      1. 8.5.1 Temperature Data Format
      2. 8.5.2 Serial Bus Interface
        1. 8.5.2.1 Command Word Structure
          1. 8.5.2.1.1 Don't Care
          2. 8.5.2.1.2 CRC Enable
          3. 8.5.2.1.3 CRC Data Block Length
          4. 8.5.2.1.4 Auto Increment
          5. 8.5.2.1.5 Read/Write
          6. 8.5.2.1.6 Sub-Address
        2. 8.5.2.2 Communication
        3. 8.5.2.3 Write Operations
        4. 8.5.2.4 Read Operations
        5. 8.5.2.5 Cyclic Redundancy Check (CRC)
          1. 8.5.2.5.1 Cyclic Redundancy Check Implementation
    6. 8.6 Register Map
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.2 Serial Bus Interface

Figure 8-9 shows an overview of the TMP126-Q1 protocol. The CS pin must be taken low between communication transactions. Data is clocked out on the falling edge of the serial clock (SCLK), while data is clocked in on the rising edge of SCLK. The 16-bit write words are latched to the respective registers after the 16th rising clock edge including during burst write mode. If a software reset is enabled, the device will immediately reset after the 16th rising clock edge and will not respond to SPI communication until a new falling edge of the CS is observed. If a software reset is triggered during burst write, any data after the configuration register write will be ignored. The SIO buffer is high impedance during reset.

Each transaction with the TMP126-Q1 will consist of a command word, followed by the data block, and the optional CRC that is enabled in the command word.

Figure 8-9 TMP126-Q1 Communication Overview