SNIS209C July 2021 – June 2022 TMP126
PRODUCTION DATA
The TMP126 has an optional CRC feature to determine the integrity of the data that has been transmitted across the SPI communication interface. The CRC for the TMP126 is enabled by setting the CRC bit in the command word to 1. When enabled, the TMP126 will append a 16-bit CRC checksum to the end the data block for read transactions. The controller can then compare this checksum to their own calculation and determine if the transaction was valid. During a write transaction, the host will append the 16-bit CRC checksum. The TMP126 will compare this to its own checksum. If there is a mismatch, the TMP126 will discard the write transaction and set a CRC fault ALERT to indicate to the host that the transaction failed. The host will need to send the register settings again to correctly program the TMP126. Reading the Alert_Status register will clear the CRC_Fault bit and de-assert the ALERT pin.
An overview of a CRC enabled write transaction is shown below with a data block length of 2.
An overview of a CRC enabled read transaction is shown below with a data block length of 2.