SBOSA45C february 2022 – may 2023 TMP1826
PRODUCTION DATA
To reduce the wire count, the bus powered mode for the TMP1826 is the primary mode of operation. The VDD pin of the device must be connected to GND and the SDQ pin of the device must be connected to the host GPIO with a pullup resistor.
To calculate the pullup resistor range, substitute the value for VPUR, VOL(MAX), VIH(MIN) and IPU(MIN) in Equation 2 as the VPUR > 2.0 V.
The actual value of the pullup resistor can then be adjusted based on the speed of communication and bus or cable parasitic capacitance.
When the VDD is activated, the TMP1826 draws current through the pullup resistor to charge its internal capacitors. When the internal capacitor is charged to the pullup voltage, the host can start communication. The bus idle state is high, which is maintained by the pullup resistor, when the host puts its GPIO in high impedance state.
The TMP1826 uses the stored charge to operate when the SDQ pin is low and measures the low period to decode bus reset, logic high and logic low sent by the host. Similarly, when the host reads data from the TMP1826, it changes the state of the bus from high to low and releases the bus. Depending on whether the device has to send a logic low or logic high, the device shall either hold the bus low or release the bus immediately.