SNIS218B September   2019  – June 2022 TMP390-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TMP390-Q1 Programming Tables
      2. 7.3.2 Trip Test
      3. 7.3.3 20°C Hysteresis
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Applications Information
    2. 8.2 Typical Applications
      1. 8.2.1 Simplified Application Schematic
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 TMP390-Q1 With 10°C Hysteresis
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 One Channel Operation for Hot Trip Point up to 124°C
        1. 8.2.3.1 Application Curve
      4. 8.2.4 One Channel Operation for Cold Trip Point
        1. 8.2.4.1 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

The TMP390-Q1 is extremely simple to layout. Place the power supply bypass capacitor as close to the device as possible, and connect the capacitor as shown in Figure 10-1. Place the RSETA and RSETB resistors as close to the device as possible. Carefully consider the resistor placement to avoid additional leakage or parasitic capacitance, as this may affect the actual resistor sense value for the trip thresholds and hysteresis. If there is a possibility of moisture condensation on the SETA and SETB circuits, which may lead to additional leakage current, consider adding a conformal coating to the circuits.