SBOS835C May   2017  – October 2019 TMP464

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Two-Wire Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Temperature Measurement Data
      2. 7.3.2 Series Resistance Cancellation
      3. 7.3.3 Differential Input Capacitance
      4. 7.3.4 Sensor Fault
      5. 7.3.5 THERM Functions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SD)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Bus Overview
        2. 7.5.1.2 Bus Definitions
        3. 7.5.1.3 Serial Bus Address
        4. 7.5.1.4 Read and Write Operations
          1. 7.5.1.4.1 Single Register Reads
          2. 7.5.1.4.2 Block Register Reads
        5. 7.5.1.5 Timeout Function
        6. 7.5.1.6 High-Speed Mode
      2. 7.5.2 TMP464 Register Reset
      3. 7.5.3 Lock Register
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
        1. 7.6.1.1  Pointer Register
        2. 7.6.1.2  Local and Remote Temperature Value Registers
        3. 7.6.1.3  Software Reset Register
        4. 7.6.1.4  THERM Status Register
        5. 7.6.1.5  THERM2 Status Register
        6. 7.6.1.6  Remote Channel Open Status Register
        7. 7.6.1.7  Configuration Register
        8. 7.6.1.8  η-Factor Correction Register
        9. 7.6.1.9  Remote Temperature Offset Register
        10. 7.6.1.10 THERM Hysteresis Register
        11. 7.6.1.11 Local and Remote THERM and THERM2 Limit Registers
        12. 7.6.1.12 Block Read - Auto Increment Pointer
        13. 7.6.1.13 Lock Register
        14. 7.6.1.14 Manufacturer and Device Identification Plus Revision Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1.2 Bus Definitions

The TMP464 device has a two-wire interface that is compatible with the I2C or SMBus interface. Figure 13 through Figure 18 illustrate the timing for various operations on the TMP464 device. The bus definitions are as follows:

    Bus Idle:Both SDA and SCL lines remain high.
    Start Data Transfer:A change in the state of the SDA line (from high to low) when the SCL line is high defines a start condition. Each data transfer initiates with a start condition.
    Stop Data Transfer:A change in the state of the SDA line (from low to high) when the SCL line is high defines a stop condition. Each data transfer terminates with a repeated start or stop condition.
    Data Transfer:The number of data bytes transferred between a start and stop condition is not limited and is determined by the master device. The receiver acknowledges the data transfer.
    Acknowledge:Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Take setup and hold times into account. On a master receive, data transfer termination can be signaled by the master generating a not-acknowledge on the last byte that is transmitted by the slave.
TMP464 Tmng_PtSet.gifFigure 13. Two-Wire Timing Diagram for Write Pointer Byte
TMP464 Tmng_PtSt2ByWr_SBOS762.gifFigure 14. Two-Wire Timing Diagram for Write Pointer Byte and Value Word
TMP464 Tmng_PtSt1ByRd_SBOS762.gif
1. The master must leave SDA high to terminate a single-byte read operation.
Figure 15. Two-Wire Timing Diagram for Pointer Set Followed by a Repeat Start and Single-Byte Read Format
TMP464 Tmng_PtSt2ByRd_v2_SBOS762.gifFigure 16. Two-Wire Timing Diagram for Pointer Byte Set Followed by a Repeat Start and Word (Two-Byte) Read
TMP464 Tmng_PtSt4ByRd_SBOS762.gifFigure 17. Two-Wire Timing Diagram for Pointer Byte Set Followed by a Repeat Start and Multiple-Word (N-Word) Read
TMP464 Tmng_MultByRd.gifFigure 18. Two-Wire Timing Diagram for Multiple-Word (N-Word) Read Without a Pointer Byte Set