SBOS721B October   2014  – October 2024 TMP75B-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 Temperature Limits and Alert
      3. 7.3.3 Serial Interface
        1. 7.3.3.1  Bus Overview
        2. 7.3.3.2  Serial Bus Address
        3. 7.3.3.3  Writing and Reading Operation
        4. 7.3.3.4  Target-Mode Operations
          1. 7.3.3.4.1 Target Receiver Mode:
          2. 7.3.3.4.2 Target Transmitter Mode:
        5. 7.3.3.5  SMBus Alert Function
        6. 7.3.3.6  General Call
        7. 7.3.3.7  High-Speed (Hs) Mode
        8. 7.3.3.8  Timeout Function
        9. 7.3.3.9  Two-Wire Timing
        10. 7.3.3.10 Two-Wire Timing Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous-Conversion Mode
      2. 7.4.2 Shutdown Mode
      3. 7.4.3 One-Shot Mode
    5. 7.5 Programming
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power-Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Temperature Limits and Alert

The temperature limits are stored in the TLOW and THIGH registers (Table 8-4 and Table 8-5) in the same format as the temperature result, and the values are compared to the temperature result on every conversion. The outcome of the comparison drives the behavior of the ALERT pin, which can operate as a comparator output or an interrupt, and is set by the TM bit in the configuration register (Table 8-3).

In comparator mode (TM = 0, default), the ALERT pin becomes active when the temperature is equal to or exceeds the value in THIGH (fault conditions) for a consecutive number of conversions as set by the FQ bits of the configuration register. ALERT clears when the temperature falls below TLOW for the same consecutive number of conversions. The difference between the two limits acts as a hysteresis on the comparator output, and a fault counter prevents false alerts as a result of environmental noise.

In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value in THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs, or the device successfully responds to the SMBus alert response address. The ALERT pin is also cleared if the device is placed in shutdown mode (see the Shutdown Mode section for shutdown mode description). After the ALERT pin is cleared, this pin becomes active again only when the temperature falls below TLOW for a consecutive number of fault conditions, and remains active until cleared by a read operation of any register, or a successful response to the SMBus alert response address. After the ALERT pin is cleared, the cycle repeats with the ALERT pin becoming active when the temperature equals or exceeds THIGH, and so on. The ALERT pin can also be cleared by resetting the device with the general-call reset command. This action also clears the state of the internal registers in the device and the fault counter memory, returning the device to comparator mode (TM = 0).

The active state of the ALERT pin is set by the POL bit in the configuration register. When POL = 0 (default), the ALERT pin is active low. When POL = 1, the ALERT pin is active high. The operation of the ALERT pin in various modes is shown in Figure 7-1.

TMP75B-Q1 ALERT Pin Modes of Operation Figure 7-1 ALERT Pin Modes of Operation