SPRS727C August   2012  – April 2014 TMS320C5517

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. 4.2.1  Oscillator and PLL
      2. 4.2.2  Real-Time Clock (RTC)
      3. 4.2.3  RESET, Interrupts, and JTAG
      4. 4.2.4  External Memory Interface (EMIF)
      5. 4.2.5  Inter-Integrated Circuit (I2C)
      6. 4.2.6  Inter-IC Sound (I2S)
      7. 4.2.7  Multichannel Buffered Serial Port (McBSP)
      8. 4.2.8  Multichannel Serial Port Interface (McSPI)
      9. 4.2.9  Serial Peripheral Interface (SPI)
      10. 4.2.10 Universal Asynchronous Receiver and Transmitter (UART)
      11. 4.2.11 Universal Serial Bus (USB) 2.0
      12. 4.2.12 Universal Host-Port Interface (UHPI)
      13. 4.2.13 MultiMedia Card (MMC)
      14. 4.2.14 Successive Approximation (SAR) Analog-to-Digital Converter (ADC)
      15. 4.2.15 General-Purpose Input and Output (GPIO)
      16. 4.2.16 Regulators and Power Management
      17. 4.2.17 Supply Voltage
      18. 4.2.18 Ground
    3. 4.3 Pin Multiplexing
      1. 4.3.1 UHPI, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing [EBSR.PPMODE Bits]
      2. 4.3.2 MMC1, McSPI, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]
      3. 4.3.3 MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]
      4. 4.3.4 EMIF EM_A[20:15] and GP[26:21] Pin Multiplexing [EBSR.Axx_MODE bits]
    4. 4.4 Connections for Unused Signals
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Electrical Characteristics
      1. 5.3.1 Power Consumption
      2. 5.3.2 Electrical Characteristics
    4. 5.4 Handling Ratings
    5. 5.5 Thermal Characteristics
    6. 5.6 Power-On Hours
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  Parameter Information
        1. 5.7.1.1 1.8-V, 2.75-V, and 3.3-V Signal Transition Levels
        2. 5.7.1.2 3.3-V Signal Transition Rates
        3. 5.7.1.3 Timing Parameters and Board Routing Analysis
      2. 5.7.2  Power Supplies
        1. 5.7.2.1 Power Considerations
          1. 5.7.2.1.1 LDO Configuration
            1. 5.7.2.1.1.1 LDO Inputs
            2. 5.7.2.1.1.2 LDO Outputs
              1. 5.7.2.1.1.2.1 LDO Control
        2. 5.7.2.2 Power-Supply Sequencing
        3. 5.7.2.3 Digital I/O Behavior When Core Power (CVDD) is Down
        4. 5.7.2.4 Power-Supply Design Considerations
        5. 5.7.2.5 Power-Supply Decoupling
        6. 5.7.2.6 LDO Input Decoupling
        7. 5.7.2.7 LDO Output Decoupling
      3. 5.7.3  Reset
        1. 5.7.3.1 Power-On Reset (POR) Circuits
          1. 5.7.3.1.1 RTC Power-On Reset (POR)
          2. 5.7.3.1.2 Main Power-On Reset (POR)
          3. 5.7.3.1.3 Reset Pin (RESET)
        2. 5.7.3.2 Pin Behavior at Reset
        3. 5.7.3.3 Reset Electrical Data and Timing
        4. 5.7.3.4 Configurations at Reset
          1. 5.7.3.4.1 Device and Peripheral Configurations at Device Reset
          2. 5.7.3.4.2 BootMode Implementation and Requirements
        5. 5.7.3.5 Configurations After Reset
          1. 5.7.3.5.1 External Bus Selection Register (EBSR)
          2. 5.7.3.5.2 LDO Control Register [7004h]
          3. 5.7.3.5.3 EMIF and USB System Control Registers (ESCR and USBSCR) [1C33h and 1C32h]
          4. 5.7.3.5.4 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]
          5. 5.7.3.5.5 Pullup and Pulldown Inhibit Registers (PUDINHIBR1, 2, 3, 4, 5, 6, and 7) [1C17h, 1C18h, 1C19h, 1C4Ch, 1C4Dh, 1C4Fh, and 1C50h, respectively]
          6. 5.7.3.5.6 Output Slew Rate Control Register (OSRCR) [1C16h]
      4. 5.7.4  Clock Specifications
        1. 5.7.4.1 Recommended Clock and Control Signal Transition Behavior
        2. 5.7.4.2 Clock Considerations
          1. 5.7.4.2.1 Clock Configurations After Device Reset
            1. 5.7.4.2.1.1 Device Clock Frequency
            2. 5.7.4.2.1.2 Peripheral Clock State
            3. 5.7.4.2.1.3 USB Oscillator Control
        3. 5.7.4.3 PLLs
          1. 5.7.4.3.1 PLL Device-Specific Information
          2. 5.7.4.3.2 Clock PLL Considerations With External Clock Sources
          3. 5.7.4.3.3 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins
            1. 5.7.4.3.3.1 USB On-Chip Oscillator With External Crystal
            2. 5.7.4.3.3.2 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal
            3. 5.7.4.3.3.3 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)
        4. 5.7.4.4 Input and Output Clocks Electrical Data and Timing
        5. 5.7.4.5 Wake-up Events, Interrupts, and XF
          1. 5.7.4.5.1 Interrupts Electrical Data and Timing
          2. 5.7.4.5.2 Wake-Up From IDLE Electrical Data and Timing
          3. 5.7.4.5.3 XF Electrical Data and Timing
      5. 5.7.5  Direct Memory Access (DMA) Controller
        1. 5.7.5.1 DMA Channel Synchronization Events
      6. 5.7.6  External Memory Interface (EMIF)
        1. 5.7.6.1 EMIF Asynchronous Memory Support
        2. 5.7.6.2 EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported
        3. 5.7.6.3 EMIF Electrical Data and Timing CVDD = 1.05 V, DVDDEMIF = 3.3/2.75/1.8 V
        4. 5.7.6.4 EMIF Electrical Data and Timing CVDD = 1.3/1.4 V, DVDDEMIF = 3.3/2.75/1.8 V
      7. 5.7.7  General-Purpose Input/Output (GPIO)
        1. 5.7.7.1 GPIO Peripheral Input/Output Electrical Data and Timing
        2. 5.7.7.2 GPIO Peripheral Input Latency Electrical Data and Timing
      8. 5.7.8  Inter-Integrated Circuit (I2C)
        1. 5.7.8.1 I2C Electrical Data and Timing
      9. 5.7.9  Inter-IC Sound (I2S)
        1. 5.7.9.1 Inter-IC Sound (I2S) Electrical Data and Timing
      10. 5.7.10 Multichannel Serial Port Interface (McSPI)
        1. 5.7.10.1 McSPI Electrical Data and Timing
          1. 5.7.10.1.1 McSPI in Slave Mode
          2. 5.7.10.1.2 McSPI in Master Mode
      11. 5.7.11 Multichannel Buffered Serial Port (McBSP)
        1. 5.7.11.1 McBSP Electrical Data and Timing
      12. 5.7.12 Multimedia Card and Secure Digital (eMMC, MMC, SD, and SDHC)
        1. 5.7.12.1 MMC and SD Electrical Data and Timing
      13. 5.7.13 Real-Time Clock (RTC)
        1. 5.7.13.1 RTC Electrical Data and Timing
      14. 5.7.14 SAR ADC (10-Bit)
        1. 5.7.14.1 SAR ADC Electrical Data and Timing
      15. 5.7.15 Serial Port Interface (SPI)
        1. 5.7.15.1 SPI Electrical Data and Timing
      16. 5.7.16 Timers
      17. 5.7.17 Universal Asynchronous Receiver and Transmitter (UART)
        1. 5.7.17.1 UART Electrical Data and Timing [Receive and Transmit]
      18. 5.7.18 Universal Host-Port Interface (UHPI)
        1. 5.7.18.1 UHPI Electrical Data and Timing
      19. 5.7.19 Universal Serial Bus (USB) 2.0 Controller
        1. 5.7.19.1 USB 2.0 Electrical Data and Timing
      20. 5.7.20 Emulation and Debug
        1. 5.7.20.1 Debugging Considerations
          1. 5.7.20.1.1 Pullup and Pulldown Resistors
          2. 5.7.20.1.2 Bus Holders
          3. 5.7.20.1.3 CLKOUT Pin
      21. 5.7.21 IEEE 1149.1 JTAG
        1. 5.7.21.1 JTAG Test_port Electrical Data and Timing
  6. 6Detailed Description
    1. 6.1 CPU
    2. 6.2 Memory
      1. 6.2.1 Internal Memory
        1. 6.2.1.1 On-Chip Dual-Access RAM (DARAM)
        2. 6.2.1.2 On-Chip Single-Access RAM (SARAM)
        3. 6.2.1.3 On-Chip Read-Only Memory (ROM)
        4. 6.2.1.4 I/O Memory
      2. 6.2.2 External Memory
      3. 6.2.3 Memory Map
      4. 6.2.4 Register Map
        1. 6.2.4.1  DMA Peripheral Register Description
        2. 6.2.4.2  EMIF Peripheral Register Description
        3. 6.2.4.3  GPIO Peripheral Register Description
        4. 6.2.4.4  I2C Peripheral Register Description
        5. 6.2.4.5  I2S Peripheral Register Description
        6. 6.2.4.6  McBSP Peripheral Register Descriptions
        7. 6.2.4.7  McSPI Peripheral Register Descriptions
        8. 6.2.4.8  MMC and SD Peripheral Register Description
        9. 6.2.4.9  RTC Peripheral Register Description
        10. 6.2.4.10 SAR ADC Peripheral Register Description
        11. 6.2.4.11 SPI Peripheral Register Descriptions
        12. 6.2.4.12 System Registers
        13. 6.2.4.13 Timers Peripheral Register Description
        14. 6.2.4.14 UART Peripheral Register Description
        15. 6.2.4.15 UHPI Peripheral Register Descriptions
        16. 6.2.4.16 USB2.0 Peripheral Register Descriptions
    3. 6.3 Identification
      1. 6.3.1 JTAG Identification
    4. 6.4 Boot Modes
      1. 6.4.1 Invocation Sequence
      2. 6.4.2 DSP Resources Used By the Bootloader
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCH|196
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Device Comparison

Table 3-1 provides characteristics of the C5517 processor.

The table shows significant features of the devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. For more detailed information on the actual device part number and maximum device operating frequency, see Section 7.1.2, Device Nomenclature.

Table 3-1 Characteristics of the Processor

HARDWARE FEATURES C5517
External Memory Interface (EMIF) Asynchronous (8- and 16-bit bus width) SRAM,
Flash (NOR, NAND),
SDRAM and Mobile SDRAM (16-bit bus width)(2)
Peripherals
Not all peripheral pins are available at the same time (for more detail, see Section 5). 		DMA Four DMA controllers each with four channels,
for a total of 16 channels
Timers

2 32-Bit General-Purpose (GP) Timers

1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog

Each timer is capable of selecting its clock source among the choices of:

  • External from a GPIO pin
  • System PLL
  • 12.00 MHz USB oscillator
UART 1 (with RTS and CTS flow control)
SPI 1 with 4 chip selects (Master only)
McSPI 1 (Master and Slave synchronous serial bus) with 3 chip selects
UHPI 1 (A configurable 16-bit multiplexed host port interface)
I2C 1 (Master and Slave)
I2S 3 (Two Channel, Full Duplex Communication)
USB 2.0 High- and Full-Speed Device (device mode only, host mode not supported)
MMC and SD 2 MMC and SD, 256 byte read and write buffer, max 50-MHz clock for SD cards, and signaling for DMA transfers
McBSP 1 (with transmit and receive)
ADC (Successive Approximation [SAR]) 1 (10-bit, 4-input, 16-µs conversion time)
Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply)
FFT Hardware Accelerator 1 (Supports 8 to 1024-point 16-bit real and complex FFT)
General-Purpose Input/Output Port (GPIO) Up to 26 pins (with 1 Additional General-Purpose Output (XF) and 4 General-Purpose Outputs for Use With SAR)
On-Chip Memory Size and Organization
  • 64KB On-Chip Dual-Access RAM (DARAM)
  • 256KB On-Chip Single-Access RAM (SARAM)
  • 128KB On-Chip Single-Access ROM (SAROM)
JTAG BSDL_ID JTAGID Register
(Value is: 0x0B95 602F)		 see Figure 6-2
CPU Frequency MHz 1.05-V Core 75 MHz
1.3-V Core 175 MHz
1.4-V Core 200 MHz
Cycle Time ns 1.05-V Core 13.3 ns
1.3-V Core 5.71 ns
1.4-V Core 5 ns
Voltage Core (V) 1.05 V (75 MHz)
1.3 V (175 MHz)
1.4 V (200 MHz)
I/O (V) 1.8 V, 2.75 V, 3.3 V
LDOs DSP_LDO

1.3 V or 1.05 V, 250 mA max current for the digital core (to be used only to supply CVDD).

Cannot be used to drive CVDD at the 1.4 V (>200 MHz) operating range.
ANA_LDO 1.3 V, 4 mA max current for SAR and power management circuits (to be used only to supply VDDA_ANA)
USB_LDO 1.3 V, 25 mA max current for USB core digital and PHY circuits (to be used only to supply USB_VDD1P3 and USB_VDDA1P3)
Temperature Commercial Temperature (default) TMS320C5517AZCH20
Industrial Temperature TMS320C5517AZCHA20
PLL Phase Lock Loop 1 (Software Programmable PLL)
BGA Package 10 x 10 mm 196-Terminal BGA (ZCH), 0.65-mm Pitch
Product Status(1) Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
(2) For more information on SDRAM devices support, see Section 5.7.6, External Memory Interface (EMIF).