SPRS737C August   2011  – April 2014 TMS320C5532 , TMS320C5533 , TMS320C5534 , TMS320C5535

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. 4.2.1  Oscillator and PLL
      2. 4.2.2  Real-Time Clock (RTC)
      3. 4.2.3  RESET, Interrupts, and JTAG
      4. 4.2.4  Inter-Integrated Circuit (I2C)
      5. 4.2.5  Inter-IC Sound (I2S)
      6. 4.2.6  Serial Peripheral Interface (SPI)
      7. 4.2.7  Universal Asynchronous Receiver/Transmitter (UART)
      8. 4.2.8  Universal Serial Bus (USB) 2.0
      9. 4.2.9  LCD Bridge
      10. 4.2.10 Secure Digital (SD)
        1. 4.2.10.1 SD1 Signal Descriptions
        2. 4.2.10.2 SD0 Signal Descriptions
      11. 4.2.11 Successive Approximation (SAR) Analog-to-Digital Converter (ADC)
      12. 4.2.12 General-Purpose Input/Output (GPIO)
      13. 4.2.13 Regulators and Power Management
      14. 4.2.14 Reserved and No Connects
      15. 4.2.15 Supply Voltage
      16. 4.2.16 Ground
    3. 4.3 Pin Multiplexing
      1. 4.3.1 LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing [EBSR.PPMODE Bits] — C5535 Only
      2. 4.3.2 SD1, I2S1, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]
      3. 4.3.3 SD0, I2S0, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Electrical Characteristics
    4. 5.4 Handling Ratings
    5. 5.5 Thermal Characteristics
    6. 5.6 Power-On Hours
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  Parameter Information
        1. 5.7.1.1 1.8-V, 2.5-V, 2.75-V, and 3.3-V Signal Transition Levels
        2. 5.7.1.2 3.3-V Signal Transition Rates
        3. 5.7.1.3 Timing Parameters and Board Routing Analysis
      2. 5.7.2  Power Supplies
        1. 5.7.2.1 Power Considerations for C5535 and C5534
          1. 5.7.2.1.1 LDO Configuration
            1. 5.7.2.1.1.1 LDO Inputs
            2. 5.7.2.1.1.2 LDO Outputs
            3. 5.7.2.1.1.3 LDO Control
        2. 5.7.2.2 Power Considerations for C5533
          1. 5.7.2.2.1 LDO Configuration
            1. 5.7.2.2.1.1 LDO Inputs
            2. 5.7.2.2.1.2 LDO Outputs
            3. 5.7.2.2.1.3 LDO Control
        3. 5.7.2.3 Power Considerations for C5532
          1. 5.7.2.3.1 LDO Configuration
          2. 5.7.2.3.2 LDO Inputs
          3. 5.7.2.3.3 LDO Outputs
        4. 5.7.2.4 Power-Supply Sequencing
        5. 5.7.2.5 Digital I/O Behavior When Core Power (CVDD) is Down
        6. 5.7.2.6 Power-Supply Design Considerations
        7. 5.7.2.7 Power-Supply Decoupling
        8. 5.7.2.8 LDO Input Decoupling
        9. 5.7.2.9 LDO Output Decoupling
      3. 5.7.3  Reset
        1. 5.7.3.1 Power-On Reset (POR) Circuits
          1. 5.7.3.1.1 RTC Power-On Reset (POR)
          2. 5.7.3.1.2 Main Power-On Reset (POR)
          3. 5.7.3.1.3 Reset Pin (RESET)
        2. 5.7.3.2 Pin Behavior at Reset
        3. 5.7.3.3 Reset Electrical Data and Timing
        4. 5.7.3.4 Configurations at Reset
          1. 5.7.3.4.1 Device and Peripheral Configurations at Device Reset
        5. 5.7.3.5 Configurations After Reset
          1. 5.7.3.5.1 External Bus Selection Register (EBSR)
          2. 5.7.3.5.2 LDO Control Register [7004h]
          3. 5.7.3.5.3 USB System Control Registers (USBSCR) [1C32h]
          4. 5.7.3.5.4 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]
          5. 5.7.3.5.5 Pullup and Pulldown Inhibit Registers (PDINHIBR1, 2, and 3) [1C17h, 1C18h, and 1C19h]
          6. 5.7.3.5.6 Output Slew Rate Control Register (OSRCR) [1C16h]
      4. 5.7.4  Clock Specifications
        1. 5.7.4.1 Recommended Clock and Control Signal Transition Behavior
        2. 5.7.4.2 Clock Considerations
          1. 5.7.4.2.1 Clock Configurations After Device Reset
            1. 5.7.4.2.1.1 Device Clock Frequency
            2. 5.7.4.2.1.2 Peripheral Clock State
            3. 5.7.4.2.1.3 USB Oscillator Control
        3. 5.7.4.3 PLLs
          1. 5.7.4.3.1 PLL Device-Specific Information
          2. 5.7.4.3.2 Clock PLL Considerations With External Clock Sources
          3. 5.7.4.3.3 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins
            1. 5.7.4.3.3.1 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal
            2. 5.7.4.3.3.2 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)
            3. 5.7.4.3.3.3 USB On-Chip Oscillator With External Crystal (Optional)
        4. 5.7.4.4 Input and Output Clocks Electrical Data and Timing
        5. 5.7.4.5 Wake-up Events, Interrupts, and XF
          1. 5.7.4.5.1 Interrupts Electrical Data and Timing
          2. 5.7.4.5.2 Wake Up From IDLE Electrical Data and Timing
          3. 5.7.4.5.3 XF Electrical Data and Timing
      5. 5.7.5  Direct Memory Access (DMA) Controller
        1. 5.7.5.1 DMA Channel Synchronization Events
      6. 5.7.6  General-Purpose Input/Output
        1. 5.7.6.1 GPIO Peripheral Input/Output Electrical Data and Timing
        2. 5.7.6.2 GPIO Peripheral Input Latency Electrical Data and Timing
      7. 5.7.7  General-Purpose Timers
      8. 5.7.8  Inter-Integrated Circuit (I2C)
        1. 5.7.8.1 I2C Electrical Data and Timing
      9. 5.7.9  Inter-IC Sound (I2S)
        1. 5.7.9.1 I2S Electrical Data and Timing
      10. 5.7.10 Liquid Crystal Display Controller (LCDC) — C5535 Only
        1. 5.7.10.1 LCDC Electrical Data and Timing
      11. 5.7.11 Real-Time Clock (RTC)
        1. 5.7.11.1 RTC-Only Mode
      12. 5.7.12 SAR ADC (10-Bit) — C5535 Only
        1. 5.7.12.1 SAR ADC Electrical Data and Timing
      13. 5.7.13 Secure Digital (SD)
        1. 5.7.13.1 SD Electrical Data and Timing
      14. 5.7.14 Serial Port Interface (SPI)
        1. 5.7.14.1 SPI Electrical Data and Timing
      15. 5.7.15 Universal Asynchronous Receiver/Transmitter (UART)
        1. 5.7.15.1 UART Electrical Data and Timing [Receive and Transmit]
      16. 5.7.16 Universal Serial Bus (USB) 2.0 Controller — Does Not Apply to C5532
        1. 5.7.16.1 USB 2.0 Electrical Data and Timing
      17. 5.7.17 Emulation and Debug
        1. 5.7.17.1 Debugging Considerations
          1. 5.7.17.1.1 Pullup and Pulldown Resistors
          2. 5.7.17.1.2 Bus Holders
          3. 5.7.17.1.3 CLKOUT Pin
      18. 5.7.18 IEEE 1149.1 JTAG
        1. 5.7.18.1 JTAG Test_port Electrical Data and Timing
  6. 6Detailed Description
    1. 6.1 CPU
    2. 6.2 Memory
      1. 6.2.1 Internal Memory
        1. 6.2.1.1 On-Chip Dual-Access RAM (DARAM)
        2. 6.2.1.2 On-Chip Read-Only Memory (ROM)
        3. 6.2.1.3 On-Chip Single-Access RAM (SARAM)
          1. 6.2.1.3.1 SARAM for C5535
          2. 6.2.1.3.2 SARAM for C5534
          3. 6.2.1.3.3 SARAM for C5533
        4. 6.2.1.4 I/O Memory
      2. 6.2.2 Memory Map
      3. 6.2.3 Register Map
        1. 6.2.3.1  General-Purpose Input/Output Peripheral Register Descriptions
        2. 6.2.3.2  I2C Peripheral Register Descriptions
        3. 6.2.3.3  I2S Peripheral Register Descriptions
        4. 6.2.3.4  LCDC Peripheral Register Descriptions
        5. 6.2.3.5  RTC Peripheral Register Descriptions
        6. 6.2.3.6  SAR ADC Peripheral Register Descriptions
        7. 6.2.3.7  SD Peripheral Register Descriptions
        8. 6.2.3.8  SPI Peripheral Register Descriptions
        9. 6.2.3.9  System Registers
        10. 6.2.3.10 Timers Peripheral Register Descriptions
        11. 6.2.3.11 UART Peripheral Register Descriptions
        12. 6.2.3.12 USB2.0 Peripheral Register Descriptions
    3. 6.3 Identification
      1. 6.3.1 JTAG Identification
    4. 6.4 Boot Modes
      1. 6.4.1 Invocation Sequence
      2. 6.4.2 Boot Configuration
      3. 6.4.3 DSP Resources Used By the Bootloader
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Related Links
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical Packaging and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZAY|144
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Device Comparison

Table 3-1 lists the important differences between the devices.

Table 3-1 Differences Between Devices

Device Digital Core Supply Voltage (CVDD) On-chip DARAM On-chip SARAM USB LCD Interface Tightly-Coupled FFT SAR ADC LDO
1.05 V 1.3 V
Maximum CPU Speed
TMS320C5535A05 50 MHz - 64KB 256KB √(1) √ √ √ ANA, DSP, and USB
TMS320C5535A10 50 MHz 100 MHz
TMS320C5534A05 50 MHz - 64KB 192KB √ -(2) - - ANA, DSP, and USB
TMS320C5534A10 50 MHz 100 MHz
TMS320C5533A05 50 MHz - 64KB 64KB √ - - - ANA and USB
TMS320C5533A10 50 MHz 100 MHz
TMS320C5532A05 50 MHz - 64KB 0KB - - - - ANA only
TMS320C5532A10 50 MHz 100 MHz
(1) √ — Supported
(2) - — Not supported

3.1 Device Characteristics

The following tables provide an overview of all the devices. The tables show significant features of each device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. For more detailed information on the actual device part number and maximum device operating frequency, see Section 7.1.2, Device Nomenclature.

Table 3-2 Characteristics of the C5535 Processor

HARDWARE FEATURES TMS320C5535A05, C5535A10
Peripherals
Not all peripheral pins are available at the same time (for more detail, see Section 5). 		DMA Four DMA controllers each with four channels,
for a total of 16 channels
Timers 2 32-Bit General-Purpose (GP) Timers
1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog
UART 1 (with RTS and CTS flow control)
SPI 1 with 4 chip selects
I2C 1 (Master or Slave)
I2S 4 (Two Channel, Full Duplex Communication)
USB 2.0 (Device only) High- and Full-Speed Device
SD 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers
LCD Bridge 1 (8-bit or 16-bit asynchronous parallel bus)
ADC (Successive Approximation [SAR]) 1 (10-bit, 4 -input, 16-μs conversion time)
Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply)
FFT Hardware Accelerator 1 (Supports 8 to 1024-point 16-bit real and complex FFT)
General-Purpose Input/Output Port (GPIO) 32 pins (with 1 Additional General-Purpose Output (XF) and 4 Special-Purpose Outputs for Use With SAR
Configure up to 20 pins simultaneously
On-Chip Memory Size (Bytes) 320 KB RAM, 128KB ROM
Organization
  • 64KB On-Chip Dual-Access RAM (DARAM)
  • 256KB On-Chip Single-Access RAM (SARAM)
  • 128 KB On-Chip Single-Access ROM (SAROM)
JTAG BSDL_ID JTAGID Register
(Value is: 0x1B8F E02F)		 see Figure 6-5
CPU Frequency MHz 1.05-V Core 50 MHz
1.3-V Core 100 MHz (TMS320C5535A10 only)
Cycle Time ns 1.05-V Core 20 ns
1.3-V Core 10 ns (TMS320C5535A10 only)
Voltage Core (V) 1.05 V – 50 MHz
1.3 V – 100 MHz (TMS320C5535A10 only)
I/O (V) 1.8 V, 2.5 V, 2.75 V, 3.3 V
LDOs DSP_LDO 1.3 V or 1.05 V, 250 mA max current for DSP CPU (CVDD)
ANA_LDO 1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL), SAR, and power management circuits (VDDA_ANA)
USB_LDO 1.3 V, 25 mA max current to supply power to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3)
Power Characterization Active @ Room Temp 25°C, 75% DMAC + 25% ADD 0.15 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Active @ Room Temp 25°C, 75% DMAC + 25% NOP 0.14 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) 0.26 mW @ 1.05 V
0.44 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) 0.23 mW @ 1.05 V
0.40 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) 0.15 mW @ 1.05 V
0.28 mW @ 1.3 V
PLL Options Software Programmable Multiplier x4 to x4099 multiplier
BGA Package 12 x 12 mm 144-Pin BGA (ZHH)
Product Status(1) Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Table 3-3 Characteristics of the C5534 Processor

HARDWARE FEATURES TMS320C5534A05, C5534A10
Peripherals
Not all peripheral pins are available at the same time (for more detail, see Section 5). 		DMA Four DMA controllers each with four channels, for a total of 16 channels
Timers 2 32-Bit General-Purpose (GP) Timers
1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog
UART 1 (with RTS and CTS flow control)
SPI 1 with 4 chip selects
I2C 1 (Master or Slave)
I2S 4 (Two Channel, Full Duplex Communication)
USB 2.0 (Device only) High- and Full-Speed Device
SD 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers
Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply)
General-Purpose Input/Output Port (GPIO) Up to 20 pins (with 1 Additional General-Purpose Output (XF))
On-Chip Memory Size (Bytes) 256KB RAM, 128KB ROM
Organization
  • 64KB On-Chip Dual-Access RAM (DARAM)
  • 192KB On-Chip Single-Access RAM (SARAM)
  • 128KB On-Chip Single-Access ROM (SAROM)
JTAG BSDL_ID JTAGID Register
(Value is: 0x1B8F E02F)		 see Figure 6-5
CPU Frequency MHz 1.05-V Core 50 MHz
1.3-V Core 100 MHz (TMS320C5534A10 only)
Cycle Time ns 1.05-V Core 20 ns
1.3-V Core 10 ns (TMS320C5534A10 only)
Voltage Core (V) 1.05 V – 50 MHz
1.3 V – 100 MHz (TMS320C5534A10 only)
I/O (V) 1.8 V, 2.5 V, 2.75 V, 3.3 V
LDOs DSP_LDO 1.3 V or 1.05 V, 250 mA max current for DSP CPU (CVDD)
ANA_LDO 1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL) and power management circuits (VDDA_ANA)
USB_LDO 1.3 V, 25 mA max current to supply power to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3)
Power Characterization Active @ Room Temp 25°C, 75% DMAC + 25% ADD 0.15 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Active @ Room Temp 25°C, 75% DMAC + 25% NOP 0.14 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) 0.26 mW @ 1.05 V
0.44 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) 0.23 mW @ 1.05 V
0.40 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) 0.15 mW @ 1.05 V
0.28 mW @ 1.3 V
PLL Options Software Programmable Multiplier x4 to x4099 multiplier
BGA Package 12 x 12 mm 144-Pin BGA (ZHH)
Product Status(1) Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Table 3-4 Characteristics of the C5533 Processor

HARDWARE FEATURES TMS320C5533A05, C5533A10
Peripherals
Not all peripheral pins are available at the same time (for more detail, see Section 5). 		DMA Four DMA controllers each with four channels,
for a total of 16 channels
Timers 2 32-Bit General-Purpose (GP) Timers
1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog
UART 1 (with RTS and CTS flow control)
SPI 1 with 4 chip selects
I2C 1 (Master or Slave)
I2S 4 (Two Channel, Full Duplex Communication)
USB 2.0 (Device only) High- and Full-Speed Device
SD 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers
Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply)
General-Purpose Input/Output Port (GPIO) Up to 20 pins (with 1 Additional General-Purpose Output (XF))
On-Chip Memory Size (Bytes) 128 KB RAM, 128KB ROM
Organization
  • 64 KB On-Chip Dual-Access RAM (DARAM)
  • 64 KB On-Chip Single-Access RAM (SARAM)
  • 128 KB On-Chip Single-Access ROM (SAROM)
JTAG BSDL_ID JTAGID Register
(Value is: 0x1B8F E02F)		 see Figure 6-5
CPU Frequency MHz 1.05-V Core 50 MHz
1.3-V Core 100 MHz (TMS320C5533A10 only)
Cycle Time ns 1.05-V Core 20 ns
1.3-V Core 10 ns (TMS320C5533A10 only)
Voltage Core (V) 1.05 V – 50 MHz
1.3 V – 100 MHz (TMS320C5533A10 only)
I/O (V) 1.8 V, 2.5 V, 2.75 V, 3.3 V
LDOs ANA_LDO 1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL) and power management circuits (VDDA_ANA)
USB_LDO 1.3 V, 25 mA max current to supply power to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3)
Power Characterization Active @ Room Temp 25°C, 75% DMAC + 25% ADD 0.15 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Active @ Room Temp 25°C, 75% DMAC + 25% NOP 0.14 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) 0.26 mW @ 1.05 V
0.44 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) 0.23 mW @ 1.05 V
0.40 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) 0.15 mW @ 1.05 V
0.28 mW @ 1.3 V
PLL Options Software Programmable Multiplier x4 to x4099 multiplier
BGA Package 12 x 12 mm 144-Pin BGA (ZHH)
Product Status(1) Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Table 3-5 Characteristics of the C5532 Processor

HARDWARE FEATURES TMS320C5532A05, C5532A10
Peripherals
Not all peripheral pins are available at the same time (for more detail, see Section 5). 		DMA Four DMA controllers each with four channels,
for a total of 16 channels
Timers 2 32-Bit General-Purpose (GP) Timers
1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog
UART 1 (with RTS and CTS flow control)
SPI 1 with 4 chip selects
I2C 1 (Master or Slave)
I2S 4 (Two Channel, Full Duplex Communication)
SD 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers
Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply)
General-Purpose Input/Output Port (GPIO) Up to 20 pins (with 1 Additional General-Purpose Output (XF))
On-Chip Memory Size (Bytes) 64KB RAM, 128KB ROM
Organization
  • 64KB On-Chip Dual-Access RAM (DARAM)
  • 128KB On-Chip Single-Access ROM (SAROM)
JTAG BSDL_ID JTAGID Register
(Value is: 0x1B8F E02F)		 see Figure 6-5
CPU Frequency MHz 1.05-V Core 50 MHz
1.3-V Core 100 MHz (TMS320C5532A10 only)
Cycle Time ns 1.05-V Core 20 ns
1.3-V Core 10 ns (TMS320C5532A10 only)
Voltage Core (V) 1.05 V – 50 MHz
1.3 V – 100 MHz (TMS320C5532A10 only)
I/O (V) 1.8 V, 2.5 V, 2.75 V, 3.3 V
LDO ANA_LDO 1.3 V, 4 mA max current for PLL (VDDA_PLL) power management circuits (VDDA_ANA)
Power Characterization Active @ Room Temp 25°C, 75% DMAC + 25% ADD 0.15 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Active @ Room Temp 25°C, 75% DMAC + 25% NOP 0.14 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) 0.26 mW @ 1.05 V
0.44 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) 0.23 mW @ 1.05 V
0.40 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) 0.15 mW @ 1.05 V
0.28 mW @ 1.3 V
PLL Options Software Programmable Multiplier x4 to x4099 multiplier
BGA Package 12 x 12 mm 144-Pin BGA (ZHH)
Product Status(1) Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.