SPRS841E March 2012 – October 2019 TMS320C6652 , TMS320C6654
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 8-14 and described in Table 8-16.
31 | 30 | 29 | 28 | 27 | 8 | 7 | 6 | 5 | 4 | 3 | 0 |
SRCC
27 |
SRCC
26 |
SRCC
25 |
SRCC
24 |
SRCC23 – SRCC4 | SRCC3 | SRCC2 | SRCC1 | SRCC0 | Reserved |
RW +0 | RW +0 | RW +0 | RW +0 | RW +0 (per bit field) | RW +0 | RW +0 | RW +0 | RW +0 | R, +0000 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
BIT | FIELD | DESCRIPTION |
---|---|---|
31-4 | SRCCx | Interrupt source acknowledgement.
Reads return current value of internal register bit. Writes:
|
3-0 | Reserved | Reserved |