SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Clock gating to each logic block is managed by the local power/sleep controllers (LPSCs) of each module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and disable the clock (or clocks) of that module at the source. For modules that share a clock with other modules, the LPSC controls the clock gating.
Table 6-6 shows the C665x clock domains.
LPSC NUMBER | MODULE(S) | NOTES |
---|---|---|
0 | Shared LPSC for all peripherals other than those listed in this table | Always on |
1 | SmartReflex | Always on |
2 | DDR3 EMIF | Always on |
3 | EMAC | Software control |
4 | VCP2_A | Software control |
5 | Debug Subsystem and Tracers | Software control |
6 | Per-core TETB and System TETB | Software control |
7 | Reserved | Reserved |
8 | Reserved | Reserved |
9 | Reserved | Reserved |
10 | PCIe | Software control |
11 | SRIO | Software control |
12 | HyperLink | Software control |
13 | Reserved | Reserved |
14 | MSMC RAM | Software control |
15 | Reserved | Reserved |
16 | Reserved | Reserved |
17 | Reserved | Reserved |
18 | Reserved | Reserved |
19 | TCP3d | Software control |
20 | VCP2_1 | Software control |
21 | Reserved | Reserved |
22 | Reserved | Reserved |
23 | C66x CorePac 0 and Timer 0 | Software control |
24 | C66x CorePac 1 (C6657 only) and Timer 1 | Software control |
No LPSC | Bootcfg, PSC, and PLL controller | These modules do not use LPSC. |