SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
NO | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
DDRCLK[P:N] | |||||
1 | tc(DDRCLKN) | Cycle time _ DDRCLKN cycle time | 3.2 | 25 | ns |
1 | tc(DDRCLKP) | Cycle time _ DDRCLKP cycle time | 3.2 | 25 | ns |
3 | tw(DDRCLKN) | Pulse width _ DDRCLKN high | 0.45*tc(DDRCLKN) | 0.55*tc(DDRCLKN) | ns |
2 | tw(DDRCLKN) | Pulse width _ DDRCLKN low | 0.45*tc(DDRCLKN) | 0.55*tc(DDRCLKN) | ns |
2 | tw(DDRCLKP) | Pulse width _ DDRCLKP high | 0.45*tc(DDRCLKP) | 0.55*tc(DDRCLKP) | ns |
3 | tw(DDRCLKP) | Pulse width _ DDRCLKP low | 0.45*tc(DDRCLKP) | 0.55*tc(DDRCLKP) | ns |
4 | tr(DDRCLK_250mv) | Transition time _ DDRCLK differential rise time (250 mV) | 50 | 350 | ps |
4 | tf(DDRCLK_250mv) | Transition time _ DDRCLK differential fall time (250 mV) | 50 | 350 | ps |
5 | tj(DDRCLKN) | Jitter, peak_to_peak _ periodic DDRCLKN | 0.025*tc(DDRCLKN) | ps | |
5 | tj(DDRCLKP) | Jitter, peak_to_peak _ periodic DDRCLKP | 0.025*tc(DDRCLKP) | ps |