SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
HARDWARE FEATURES | TMS320C6655 | TMS320C6657 | |
---|---|---|---|
Peripheral | DDR3 Memory Controller (32-bit bus width) [1.5 V I/O] (clock source = DDRREFCLKN|P) | 1 | |
DDR3 Maximum Data Rate | 1333 | ||
EDMA3 (64 independent channels) [DSP/3 clock rate] | 1 | ||
High-speed 1×/2×/4× Serial RapidIO Port (four lanes) | 1 | ||
PCIe (two lanes) | 1 | ||
10/100/1000 Ethernet | 1 | ||
Management Data Input/Output (MDIO) | 1 | ||
HyperLink | 1 | ||
EMIF16 | 1 | ||
McBSP | 2 | ||
SPI | 1 | ||
UART | 2 | ||
uPP | 1 | ||
I2C | 1 | ||
64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency) | 8 (each configurable as two 32-bit timers) | ||
General-Purpose Input/Output port (GPIO) | 32 | ||
Encoder/Decoder
Coprocessors |
VCP2 (clock source = CPU/3 clock frequency) | 2 | |
TCP3d (clock source = CPU/2 clock frequency) | 1 | ||
On-Chip Memory | CorePac Memory | 32KB L1 Program Memory [SRAM/Cache]
32KB L1 Data Memory [SRAM/Cache] 1024KB L2 Unified Memory/Cache |
|
ROM Memory | 128KB L3 ROM | ||
Multicore Shared Memory | 1024KB MSM SRAM | ||
C66x CorePac
Revision ID |
CorePac Revision ID Register
(address location: 0181 2000h) |
See Section 7.5. | |
JTAG BSDL_ID | JTAGID register (address location: 0262 0018h) | See Section 8.3.3. | |
Frequency | MHz | 1250 (1.25 GHz) | |
Cycle Time | ns | 0.8 (1.25 GHz) | |
Extended Case Temp | –40ºC to 100ºC | –40ºC to 100ºC | |
Voltage | Core (V) | SmartReflex™ variable supply | |
I/O (V) | 1.0 V, 1.5 V, and 1.8 V | ||
Process Technology | µm | 0.040 µm | |
BGA Package | 21 mm × 21 mm, 0.80 mm pitch | 625-Pin Flip-Chip Plastic BGA (CZH or GZH) | |
Product Status(1) | Production Data (PD) | PD | PD |