SPRS814D March   2012  – October 2019 TMS320C6655 , TMS320C6657

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Device Comparison
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Terminal Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for [CZH/GZH] Package
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  SmartReflex
        1. Table 5-1 SmartReflex 4-Pin VID Interface Switching Characteristics
      2. 5.7.2  Reset Electrical Data / Timing
        1. Table 5-2 Reset Timing Requirements
        2. Table 5-3 Reset Switching Characteristics Over Recommended Operating Conditions
        3. Table 5-4 Boot Configuration Timing Requirements
      3. 5.7.3  Main PLL Stabilization, Lock, and Reset Times
      4. 5.7.4  Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
        1. Table 5-6 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements
      5. 5.7.5  DDR3 PLL Input Clock Electrical Data/Timing
        1. Table 5-7 DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
      6. 5.7.6  External Interrupts Electrical Data/Timing
        1. Table 5-8 NMI and Local Reset Timing Requirements
      7. 5.7.7  DDR3 Memory Controller Electrical Data/Timing
      8. 5.7.8  I2C Electrical Data/Timing
        1. 5.7.8.1 Inter-Integrated Circuits (I2C) Timing
          1. Table 5-9  I2C Timing Requirements
          2. Table 5-10 I2C Switching Characteristics
      9. 5.7.9  SPI Peripheral
        1. 5.7.9.1 SPI Timing
          1. Table 5-11 SPI Timing Requirements
          2. Table 5-12 SPI Switching Characteristics
      10. 5.7.10 HyperLink Electrical Data/Timing
        1. Table 5-13 HyperLink Peripheral Timing Requirements
        2. Table 5-14 HyperLink Peripheral Switching Characteristics
      11. 5.7.11 UART Peripheral
        1. Table 5-15 UART Timing Requirements
        2. Table 5-16 UART Switching Characteristics
      12. 5.7.12 EMIF16 Peripheral
        1. 5.7.12.1 EMIF16 Electrical Data/Timing
          1. Table 5-17 EMIF16 Asynchronous Memory Timing Requirements
      13. 5.7.13 MDIO Timing
        1. Table 5-18 MDIO Timing Requirements
        2. Table 5-19 MDIO Switching Characteristics
      14. 5.7.14 Timers Electrical Data/Timing
        1. Table 5-20 Timer Input Timing Requirements
        2. Table 5-21 Timer Output Switching Characteristics
      15. 5.7.15 General-Purpose Input/Output (GPIO)
        1. 5.7.15.1 GPIO Device-Specific Information
        2. 5.7.15.2 GPIO Electrical Data/Timing
          1. Table 5-22 GPIO Input Timing Requirements
          2. Table 5-23 GPIO Output Switching Characteristics
      16. 5.7.16 McBSP Electrical Data/Timing
        1. 5.7.16.1 McBSP Timing
          1. Table 5-24 McBSP Timing Requirements
          2. Table 5-25 McBSP Switching Characteristics
          3. Table 5-26 McBSP Timing Requirements for FSR When GSYNC = 1
      17. 5.7.17 uPP Timing and Switching
        1. Table 5-27 uPP Timing Requirements
        2. Table 5-28 uPP Switching Characteristics
      18. 5.7.18 Trace Electrical Data/Timing
        1. Table 5-29 DSP Trace Switching Characteristics
        2. Table 5-30 STM Trace Switching Characteristics
      19. 5.7.19 JTAG Electrical Data/Timing
        1. Table 5-31 JTAG Test Port Timing Requirements
        2. Table 5-32 JTAG Test Port Switching Characteristics
  6. 6 Detailed Description
    1. 6.1  Recommended Clock and Control Signal Transition Behavior
    2. 6.2  Power Supplies
      1. 6.2.1 Power Supply to Peripheral I/O Mapping
      2. 6.2.2 Power-Supply Sequencing
        1. 6.2.2.1 Core-Before-IO Power Sequencing
        2. 6.2.2.2 IO-Before-Core Power Sequencing
        3. 6.2.2.3 Prolonged Resets
        4. 6.2.2.4 Clocking During Power Sequencing
      3. 6.2.3 Power-Down Sequence
      4. 6.2.4 Power Supply Decoupling and Bulk Capacitors
    3. 6.3  Power Sleep Controller (PSC)
      1. 6.3.1 Power Domains
      2. 6.3.2 Clock Domains
      3. 6.3.3 PSC Register Memory Map
    4. 6.4  Reset Controller
      1. 6.4.1 Power-on Reset
      2. 6.4.2 Hard Reset
      3. 6.4.3 Soft Reset
      4. 6.4.4 Local Reset
      5. 6.4.5 Reset Priority
      6. 6.4.6 Reset Controller Register
    5. 6.5  Main PLL and PLL Controller
      1. 6.5.1 Main PLL Controller Device-Specific Information
        1. 6.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 6.5.1.2 Main PLL Controller Operating Modes
      2. 6.5.2 PLL Controller Memory Map
        1. 6.5.2.1 PLL Secondary Control Register (SECCTL)
          1. Table 6-10 PLL Secondary Control Register (SECCTL) Field Descriptions
        2. 6.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
          1. Table 6-11 PLL Controller Divider Register (PLLDIVn) Field Descriptions
        3. 6.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
          1. Table 6-12 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
        4. 6.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
          1. Table 6-13 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
        5. 6.5.2.5 SYSCLK Status Register (SYSTAT)
          1. Table 6-14 SYSCLK Status Register (SYSTAT) Field Descriptions
        6. 6.5.2.6 Reset Type Status Register (RSTYPE)
          1. Table 6-15 Reset Type Status Register (RSTYPE) Field Descriptions
        7. 6.5.2.7 Reset Control Register (RSTCTRL)
          1. Table 6-16 Reset Control Register (RSTCTRL) Field Descriptions
        8. 6.5.2.8 Reset Configuration Register (RSTCFG)
          1. Table 6-17 Reset Configuration Register (RSTCFG) Field Descriptions
        9. 6.5.2.9 Reset Isolation Register (RSISO)
          1. Table 6-18 Reset Isolation Register (RSISO) Field Descriptions
      3. 6.5.3 Main PLL Control Register
        1. Table 6-19 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
        2. Table 6-20 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
      4. 6.5.4 Main PLL and PLL Controller Initialization Sequence
    6. 6.6  DDR3 PLL
      1. 6.6.1 DDR3 PLL Control Register
        1. Table 6-21 DDR3 PLL Control Register 0 Field Descriptions
        2. Table 6-22 DDR3 PLL Control Register 1 Field Descriptions
      2. 6.6.2 DDR3 PLL Device-Specific Information
      3. 6.6.3 DDR3 PLL Initialization Sequence
    7. 6.7  Enhanced Direct Memory Access (EDMA3) Controller
      1. 6.7.1 EDMA3 Device-Specific Information
      2. 6.7.2 EDMA3 Channel Controller Configuration
      3. 6.7.3 EDMA3 Transfer Controller Configuration
      4. 6.7.4 EDMA3 Channel Synchronization Events
    8. 6.8  Interrupts
      1. 6.8.1 Interrupt Sources and Interrupt Controller
      2. 6.8.2 CIC Registers
        1. 6.8.2.1 CIC0 Register Map
        2. 6.8.2.2 CIC1 Register Map
        3. 6.8.2.3 CIC2 Register Map
      3. 6.8.3 Interprocessor Register Map
      4. 6.8.4 NMI and LRESET
    9. 6.9  Memory Protection Unit (MPU)
      1. 6.9.1 MPU Registers
        1. 6.9.1.1 MPU Register Map
        2. 6.9.1.2 Device-Specific MPU Registers
          1. 6.9.1.2.1 Configuration Register (CONFIG)
            1. Table 6-44 Configuration Register (CONFIG) Field Descriptions
      2. 6.9.2 MPU Programmable Range Registers
        1. 6.9.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
          1. Table 6-45 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions
        2. 6.9.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
          1. Table 6-46 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions
        3. 6.9.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
          1. Table 6-47 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
        4. 6.9.2.4 MPU Registers Reset Values
    10. 6.10 DDR3 Memory Controller
      1. 6.10.1 DDR3 Memory Controller Device-Specific Information
    11. 6.11 I2C Peripheral
      1. 6.11.1 I2C Device-Specific Information
      2. 6.11.2 I2C Peripheral Register Description(s)
    12. 6.12 HyperLink Peripheral
      1. 6.12.1 HyperLink Device-Specific Interrupt Event
    13. 6.13 PCIe Peripheral
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Device-Specific Information
      2. 6.14.2 EMAC Peripheral Register Description(s)
      3. 6.14.3 EMAC Electrical Data/Timing (SGMII)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Peripheral Registers
    16. 6.16 Timers
      1. 6.16.1 Timers Device-Specific Information
    17. 6.17 Semaphore2
    18. 6.18 Multichannel Buffered Serial Port (McBSP)
      1. 6.18.1 McBSP Peripheral Register
    19. 6.19 Universal Parallel Port (uPP)
      1. 6.19.1 uPP Register Descriptions
    20. 6.20 Serial RapidIO (SRIO) Port
    21. 6.21 Turbo Decoder Coprocessor (TCP3d)
    22. 6.22 Enhanced Viterbi-Decoder Coprocessor (VCP2)
    23. 6.23 Emulation Features and Capability
      1. 6.23.1 Advanced Event Triggering (AET)
      2. 6.23.2 Trace
      3. 6.23.3 IEEE 1149.1 JTAG
        1. 6.23.3.1 IEEE 1149.1 JTAG Compatibility Statement
    24. 6.24 DSP Core Description
    25. 6.25 Memory Map Summary
    26. 6.26 Boot Sequence
    27. 6.27 Boot Modes Supported and PLL Settings
      1. 6.27.1 Boot Device Field
        1. Table 6-64 Boot Mode Pins: Boot Device Values
      2. 6.27.2 Device Configuration Field
        1. 6.27.2.1 EMIF16 / UART / No Boot Device Configuration
          1. Table 6-65 EMIF16 / UART / No Boot Configuration Field Descriptions
          2. 6.27.2.1.1 No Boot Mode
            1. Table 6-66 No Boot Configuration Field Descriptions
          3. 6.27.2.1.2 UART Boot Mode
            1. Table 6-67 UART Boot Configuration Field Descriptions
          4. 6.27.2.1.3 EMIF16 Boot Mode
            1. Table 6-68 EMIF16 Boot Configuration Field Descriptions
        2. 6.27.2.2 Serial Rapid I/O Boot Device Configuration
          1. Table 6-69 Serial Rapid I/O Configuration Field Descriptions
        3. 6.27.2.3 Ethernet (SGMII) Boot Device Configuration
          1. Table 6-70 Ethernet (SGMII) Configuration Field Descriptions
        4. 6.27.2.4 NAND Boot Device Configuration
          1. Table 6-71 NAND Configuration Field Descriptions
        5. 6.27.2.5 PCI Boot Device Configuration
          1. Table 6-72 PCI Device Configuration Field Descriptions
        6. 6.27.2.6 I2C Boot Device Configuration
          1. 6.27.2.6.1 I2C Master Mode
            1. Table 6-74 I2C Master Mode Device Configuration Field Descriptions
          2. 6.27.2.6.2 I2C Passive Mode
            1. Table 6-75 I2C Passive Mode Device Configuration Field Descriptions
        7. 6.27.2.7 SPI Boot Device Configuration
          1. Table 6-76 SPI Device Configuration Field Descriptions
        8. 6.27.2.8 HyperLink Boot Device Configuration
          1. Table 6-77 HyperLink Boot Device Configuration Field Descriptions
      3. 6.27.3 Boot Parameter Table
        1. Table 6-80 PLL Configuration Field Description
        2. 6.27.3.1   Sleep / XIP Mode Parameter Table
          1. Table 6-82 EMIF16 XIP Option Field Descriptions
        3. 6.27.3.2   SRIO Mode Boot Parameter Table
          1. Table 6-84 SRIO Boot Options Description
        4. 6.27.3.3   Ethernet Mode Boot Parameter Table
          1. Table 6-87 Ethernet Options Field Descriptions
          2. Table 6-88 SGMII Config Field Descriptions
        5. 6.27.3.4   NAND Mode Boot Parameter Table
          1. Table 6-90 NAND Boot Parameter Options Bit Field Descriptions
        6. 6.27.3.5   PCIE Mode Boot Parameter Table
          1. Table 6-92 PCIe Options Field Descriptions
        7. 6.27.3.6   I2C Mode Boot Parameter Table
          1. Table 6-94 Register Description
        8. 6.27.3.7   SPI Mode Boot Parameter Table
          1. Table 6-96 SPI Options Field Description
        9. 6.27.3.8   Hyperlink Mode Boot Parameter Table
          1. Table 6-98 Hyperlink Options Field Descriptions
        10. 6.27.3.9   UART Mode Boot Parameter Table
    28. 6.28 PLL Boot Configuration Settings
    29. 6.29 Second-Level Bootloaders
  7. 7 C66x CorePac
    1. 7.1 Memory Architecture
      1. 7.1.1 L1P Memory
      2. 7.1.2 L1D Memory
      3. 7.1.3 L2 Memory
      4. 7.1.4 MSM SRAM
      5. 7.1.5 L3 Memory
    2. 7.2 Memory Protection
    3. 7.3 Bandwidth Management
    4. 7.4 Power-Down Control
    5. 7.5 C66x CorePac Revision
      1. Table 7-2 CorePac Revision ID Register (MM_REVID) Field Descriptions
    6. 7.6 C66x CorePac Register Descriptions
  8. 8 Device Configuration
    1. 8.1 Device Configuration at Device Reset
    2. 8.2 Peripheral Selection After Device Reset
    3. 8.3 Device State Control Registers
      1. 8.3.1  Device Status Register
        1. Table 8-3 Device Status Register Field Descriptions
      2. 8.3.2  Device Configuration Register
        1. Table 8-4 Device Configuration Register Field Descriptions
      3. 8.3.3  JTAG ID (JTAGID) Register Description
        1. Table 8-5 JTAG ID Register Field Descriptions
      4. 8.3.4  Kicker Mechanism (KICK0 and KICK1) Register
      5. 8.3.5  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        1. Table 8-6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
      6. 8.3.6  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        1. Table 8-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
      7. 8.3.7  Reset Status (RESET_STAT) Register
        1. Table 8-8 Reset Status Register (RESET_STAT) Field Descriptions
      8. 8.3.8  Reset Status Clear (RESET_STAT_CLR) Register
        1. Table 8-9 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions
      9. 8.3.9  Boot Complete (BOOTCOMPLETE) Register
        1. Table 8-10 Boot Complete Register (BOOTCOMPLETE) Field Descriptions
      10. 8.3.10 Power State Control (PWRSTATECTL) Register
        1. Table 8-11 Power State Control Register (PWRSTATECTL) Field Descriptions
      11. 8.3.11 NMI Event Generation to CorePac (NMIGRx) Register
        1. Table 8-12 NMI Generation Register (NMIGRx) Field Descriptions
      12. 8.3.12 IPC Generation (IPCGRx) Registers
        1. Table 8-13 IPC Generation Registers (IPCGRx) Field Descriptions
      13. 8.3.13 IPC Acknowledgement (IPCARx) Registers
        1. Table 8-14 IPC Acknowledgement Registers (IPCARx) Field Descriptions
      14. 8.3.14 IPC Generation Host (IPCGRH) Register
        1. Table 8-15 IPC Generation Registers (IPCGRH) Field Descriptions
      15. 8.3.15 IPC Acknowledgement Host (IPCARH) Register
        1. Table 8-16 IPC Acknowledgement Register (IPCARH) Field Descriptions
      16. 8.3.16 Timer Input Selection Register (TINPSEL)
        1. Table 8-17 Timer Input Selection Field Description (TINPSEL)
      17. 8.3.17 Timer Output Selection Register (TOUTPSEL)
        1. Table 8-18 Timer Output Selection Field Description (TOUTPSEL)
      18. 8.3.18 Reset Mux (RSTMUXx) Register
        1. Table 8-19 Reset Mux Register Field Descriptions
      19. 8.3.19 Device Speed (DEVSPEED) Register
        1. Table 8-20 Device Speed Register Field Descriptions
      20. 8.3.20 Pin Control 0 (PIN_CONTROL_0) Register
        1. Table 8-21 Pin Control 0 Register Field Descriptions
      21. 8.3.21 Pin Control 1 (PIN_CONTROL_1) Register
        1. Table 8-22 Pin Control 1 Register Field Descriptions
      22. 8.3.22 uPP Clock Source (UPP_CLOCK) Register
        1. Table 8-23 uPP Clock Source Register Field Descriptions
    4. 8.4 Pullup and Pulldown Resistors
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix
    3. 9.3 TeraNet Switch Fabric Connections
    4. 9.4 Bus Priorities
      1. 9.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register
        1. Table 9-3 Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
      2. 9.4.2 EMAC / uPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register
        1. Table 9-4 EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) Field Descriptions
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Related Links
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CZH|625
  • GZH|625
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Enhanced Direct Memory Access (EDMA3) Controller

The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (for example, data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event driven peripherals, and offloads data transfers from the device CPU.

There is one EDMA Channel Controller on the C665x device: EDMA3_CC. It has four transfer controllers: TC0, TC1, TC2, and TC3. In the context of this document, TCx associated with CC is referred to as EDMA3_CC_TCx. Each of the transfer controllers has a direct connection to the switch fabric. Section 9.2 lists the peripherals that can be accessed by the transfer controllers.

The EDMA3 Channel Controller includes the following features:

  • Fully orthogonal transfer description
    • Three transfer dimensions:
      • Array (multiple bytes)
      • Frame (multiple arrays)
      • Block (multiple frames)
    • Single event can trigger transfer of array, frame, or entire block
    • Independent indexes on source and destination
  • Flexible transfer definition:
    • Increment or FIFO transfer addressing modes
    • Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous transfers, all with no CPU intervention
    • Chaining allows multiple transfers to execute with one event
  • 512 PaRAM entries
    • Used to define transfer context for channels
    • Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
  • 64 DMA channels
    • Manually triggered (CPU writes to channel controller register), external event triggered, and chain triggered (completion of one transfer triggers another)
  • Eight Quick DMA (QDMA) channels
    • Used for software-driven transfers
    • Triggered upon writing to a single PaRAM set entry
  • Four transfer controllers and four event queues with programmable system-level priority
  • Interrupt generation for transfer completion and error conditions
  • Debug visibility
    • Queue watermarking/threshold allows detection of maximum usage of event queues
    • Error and status recording to facilitate debug