SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
SGMII boot is shown in Figure 6-32 and described in Table 6-70.
9 | 8 | 7 | 6 | 5 | 4 | 3 |
SerDes Clock Mult | Ext connection | Device ID |
Bit | Field | Description |
---|---|---|
9-8 | SerDes Clock Mult | SGMII SerDes input clock. The output frequency of the PLL must be 1.25GB.
|
7-6 | Ext connection | External connection mode
|
5-3 | Device ID | This value can range from 0 to 7 is used in the device ID field of the Ethernet-ready frame. |