SPRS814D March   2012  – October 2019 TMS320C6655 , TMS320C6657

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Device Comparison
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Terminal Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for [CZH/GZH] Package
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  SmartReflex
        1. Table 5-1 SmartReflex 4-Pin VID Interface Switching Characteristics
      2. 5.7.2  Reset Electrical Data / Timing
        1. Table 5-2 Reset Timing Requirements
        2. Table 5-3 Reset Switching Characteristics Over Recommended Operating Conditions
        3. Table 5-4 Boot Configuration Timing Requirements
      3. 5.7.3  Main PLL Stabilization, Lock, and Reset Times
      4. 5.7.4  Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
        1. Table 5-6 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements
      5. 5.7.5  DDR3 PLL Input Clock Electrical Data/Timing
        1. Table 5-7 DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
      6. 5.7.6  External Interrupts Electrical Data/Timing
        1. Table 5-8 NMI and Local Reset Timing Requirements
      7. 5.7.7  DDR3 Memory Controller Electrical Data/Timing
      8. 5.7.8  I2C Electrical Data/Timing
        1. 5.7.8.1 Inter-Integrated Circuits (I2C) Timing
          1. Table 5-9  I2C Timing Requirements
          2. Table 5-10 I2C Switching Characteristics
      9. 5.7.9  SPI Peripheral
        1. 5.7.9.1 SPI Timing
          1. Table 5-11 SPI Timing Requirements
          2. Table 5-12 SPI Switching Characteristics
      10. 5.7.10 HyperLink Electrical Data/Timing
        1. Table 5-13 HyperLink Peripheral Timing Requirements
        2. Table 5-14 HyperLink Peripheral Switching Characteristics
      11. 5.7.11 UART Peripheral
        1. Table 5-15 UART Timing Requirements
        2. Table 5-16 UART Switching Characteristics
      12. 5.7.12 EMIF16 Peripheral
        1. 5.7.12.1 EMIF16 Electrical Data/Timing
          1. Table 5-17 EMIF16 Asynchronous Memory Timing Requirements
      13. 5.7.13 MDIO Timing
        1. Table 5-18 MDIO Timing Requirements
        2. Table 5-19 MDIO Switching Characteristics
      14. 5.7.14 Timers Electrical Data/Timing
        1. Table 5-20 Timer Input Timing Requirements
        2. Table 5-21 Timer Output Switching Characteristics
      15. 5.7.15 General-Purpose Input/Output (GPIO)
        1. 5.7.15.1 GPIO Device-Specific Information
        2. 5.7.15.2 GPIO Electrical Data/Timing
          1. Table 5-22 GPIO Input Timing Requirements
          2. Table 5-23 GPIO Output Switching Characteristics
      16. 5.7.16 McBSP Electrical Data/Timing
        1. 5.7.16.1 McBSP Timing
          1. Table 5-24 McBSP Timing Requirements
          2. Table 5-25 McBSP Switching Characteristics
          3. Table 5-26 McBSP Timing Requirements for FSR When GSYNC = 1
      17. 5.7.17 uPP Timing and Switching
        1. Table 5-27 uPP Timing Requirements
        2. Table 5-28 uPP Switching Characteristics
      18. 5.7.18 Trace Electrical Data/Timing
        1. Table 5-29 DSP Trace Switching Characteristics
        2. Table 5-30 STM Trace Switching Characteristics
      19. 5.7.19 JTAG Electrical Data/Timing
        1. Table 5-31 JTAG Test Port Timing Requirements
        2. Table 5-32 JTAG Test Port Switching Characteristics
  6. 6 Detailed Description
    1. 6.1  Recommended Clock and Control Signal Transition Behavior
    2. 6.2  Power Supplies
      1. 6.2.1 Power Supply to Peripheral I/O Mapping
      2. 6.2.2 Power-Supply Sequencing
        1. 6.2.2.1 Core-Before-IO Power Sequencing
        2. 6.2.2.2 IO-Before-Core Power Sequencing
        3. 6.2.2.3 Prolonged Resets
        4. 6.2.2.4 Clocking During Power Sequencing
      3. 6.2.3 Power-Down Sequence
      4. 6.2.4 Power Supply Decoupling and Bulk Capacitors
    3. 6.3  Power Sleep Controller (PSC)
      1. 6.3.1 Power Domains
      2. 6.3.2 Clock Domains
      3. 6.3.3 PSC Register Memory Map
    4. 6.4  Reset Controller
      1. 6.4.1 Power-on Reset
      2. 6.4.2 Hard Reset
      3. 6.4.3 Soft Reset
      4. 6.4.4 Local Reset
      5. 6.4.5 Reset Priority
      6. 6.4.6 Reset Controller Register
    5. 6.5  Main PLL and PLL Controller
      1. 6.5.1 Main PLL Controller Device-Specific Information
        1. 6.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 6.5.1.2 Main PLL Controller Operating Modes
      2. 6.5.2 PLL Controller Memory Map
        1. 6.5.2.1 PLL Secondary Control Register (SECCTL)
          1. Table 6-10 PLL Secondary Control Register (SECCTL) Field Descriptions
        2. 6.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
          1. Table 6-11 PLL Controller Divider Register (PLLDIVn) Field Descriptions
        3. 6.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
          1. Table 6-12 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
        4. 6.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
          1. Table 6-13 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
        5. 6.5.2.5 SYSCLK Status Register (SYSTAT)
          1. Table 6-14 SYSCLK Status Register (SYSTAT) Field Descriptions
        6. 6.5.2.6 Reset Type Status Register (RSTYPE)
          1. Table 6-15 Reset Type Status Register (RSTYPE) Field Descriptions
        7. 6.5.2.7 Reset Control Register (RSTCTRL)
          1. Table 6-16 Reset Control Register (RSTCTRL) Field Descriptions
        8. 6.5.2.8 Reset Configuration Register (RSTCFG)
          1. Table 6-17 Reset Configuration Register (RSTCFG) Field Descriptions
        9. 6.5.2.9 Reset Isolation Register (RSISO)
          1. Table 6-18 Reset Isolation Register (RSISO) Field Descriptions
      3. 6.5.3 Main PLL Control Register
        1. Table 6-19 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
        2. Table 6-20 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
      4. 6.5.4 Main PLL and PLL Controller Initialization Sequence
    6. 6.6  DDR3 PLL
      1. 6.6.1 DDR3 PLL Control Register
        1. Table 6-21 DDR3 PLL Control Register 0 Field Descriptions
        2. Table 6-22 DDR3 PLL Control Register 1 Field Descriptions
      2. 6.6.2 DDR3 PLL Device-Specific Information
      3. 6.6.3 DDR3 PLL Initialization Sequence
    7. 6.7  Enhanced Direct Memory Access (EDMA3) Controller
      1. 6.7.1 EDMA3 Device-Specific Information
      2. 6.7.2 EDMA3 Channel Controller Configuration
      3. 6.7.3 EDMA3 Transfer Controller Configuration
      4. 6.7.4 EDMA3 Channel Synchronization Events
    8. 6.8  Interrupts
      1. 6.8.1 Interrupt Sources and Interrupt Controller
      2. 6.8.2 CIC Registers
        1. 6.8.2.1 CIC0 Register Map
        2. 6.8.2.2 CIC1 Register Map
        3. 6.8.2.3 CIC2 Register Map
      3. 6.8.3 Interprocessor Register Map
      4. 6.8.4 NMI and LRESET
    9. 6.9  Memory Protection Unit (MPU)
      1. 6.9.1 MPU Registers
        1. 6.9.1.1 MPU Register Map
        2. 6.9.1.2 Device-Specific MPU Registers
          1. 6.9.1.2.1 Configuration Register (CONFIG)
            1. Table 6-44 Configuration Register (CONFIG) Field Descriptions
      2. 6.9.2 MPU Programmable Range Registers
        1. 6.9.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
          1. Table 6-45 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions
        2. 6.9.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
          1. Table 6-46 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions
        3. 6.9.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
          1. Table 6-47 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
        4. 6.9.2.4 MPU Registers Reset Values
    10. 6.10 DDR3 Memory Controller
      1. 6.10.1 DDR3 Memory Controller Device-Specific Information
    11. 6.11 I2C Peripheral
      1. 6.11.1 I2C Device-Specific Information
      2. 6.11.2 I2C Peripheral Register Description(s)
    12. 6.12 HyperLink Peripheral
      1. 6.12.1 HyperLink Device-Specific Interrupt Event
    13. 6.13 PCIe Peripheral
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Device-Specific Information
      2. 6.14.2 EMAC Peripheral Register Description(s)
      3. 6.14.3 EMAC Electrical Data/Timing (SGMII)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Peripheral Registers
    16. 6.16 Timers
      1. 6.16.1 Timers Device-Specific Information
    17. 6.17 Semaphore2
    18. 6.18 Multichannel Buffered Serial Port (McBSP)
      1. 6.18.1 McBSP Peripheral Register
    19. 6.19 Universal Parallel Port (uPP)
      1. 6.19.1 uPP Register Descriptions
    20. 6.20 Serial RapidIO (SRIO) Port
    21. 6.21 Turbo Decoder Coprocessor (TCP3d)
    22. 6.22 Enhanced Viterbi-Decoder Coprocessor (VCP2)
    23. 6.23 Emulation Features and Capability
      1. 6.23.1 Advanced Event Triggering (AET)
      2. 6.23.2 Trace
      3. 6.23.3 IEEE 1149.1 JTAG
        1. 6.23.3.1 IEEE 1149.1 JTAG Compatibility Statement
    24. 6.24 DSP Core Description
    25. 6.25 Memory Map Summary
    26. 6.26 Boot Sequence
    27. 6.27 Boot Modes Supported and PLL Settings
      1. 6.27.1 Boot Device Field
        1. Table 6-64 Boot Mode Pins: Boot Device Values
      2. 6.27.2 Device Configuration Field
        1. 6.27.2.1 EMIF16 / UART / No Boot Device Configuration
          1. Table 6-65 EMIF16 / UART / No Boot Configuration Field Descriptions
          2. 6.27.2.1.1 No Boot Mode
            1. Table 6-66 No Boot Configuration Field Descriptions
          3. 6.27.2.1.2 UART Boot Mode
            1. Table 6-67 UART Boot Configuration Field Descriptions
          4. 6.27.2.1.3 EMIF16 Boot Mode
            1. Table 6-68 EMIF16 Boot Configuration Field Descriptions
        2. 6.27.2.2 Serial Rapid I/O Boot Device Configuration
          1. Table 6-69 Serial Rapid I/O Configuration Field Descriptions
        3. 6.27.2.3 Ethernet (SGMII) Boot Device Configuration
          1. Table 6-70 Ethernet (SGMII) Configuration Field Descriptions
        4. 6.27.2.4 NAND Boot Device Configuration
          1. Table 6-71 NAND Configuration Field Descriptions
        5. 6.27.2.5 PCI Boot Device Configuration
          1. Table 6-72 PCI Device Configuration Field Descriptions
        6. 6.27.2.6 I2C Boot Device Configuration
          1. 6.27.2.6.1 I2C Master Mode
            1. Table 6-74 I2C Master Mode Device Configuration Field Descriptions
          2. 6.27.2.6.2 I2C Passive Mode
            1. Table 6-75 I2C Passive Mode Device Configuration Field Descriptions
        7. 6.27.2.7 SPI Boot Device Configuration
          1. Table 6-76 SPI Device Configuration Field Descriptions
        8. 6.27.2.8 HyperLink Boot Device Configuration
          1. Table 6-77 HyperLink Boot Device Configuration Field Descriptions
      3. 6.27.3 Boot Parameter Table
        1. Table 6-80 PLL Configuration Field Description
        2. 6.27.3.1   Sleep / XIP Mode Parameter Table
          1. Table 6-82 EMIF16 XIP Option Field Descriptions
        3. 6.27.3.2   SRIO Mode Boot Parameter Table
          1. Table 6-84 SRIO Boot Options Description
        4. 6.27.3.3   Ethernet Mode Boot Parameter Table
          1. Table 6-87 Ethernet Options Field Descriptions
          2. Table 6-88 SGMII Config Field Descriptions
        5. 6.27.3.4   NAND Mode Boot Parameter Table
          1. Table 6-90 NAND Boot Parameter Options Bit Field Descriptions
        6. 6.27.3.5   PCIE Mode Boot Parameter Table
          1. Table 6-92 PCIe Options Field Descriptions
        7. 6.27.3.6   I2C Mode Boot Parameter Table
          1. Table 6-94 Register Description
        8. 6.27.3.7   SPI Mode Boot Parameter Table
          1. Table 6-96 SPI Options Field Description
        9. 6.27.3.8   Hyperlink Mode Boot Parameter Table
          1. Table 6-98 Hyperlink Options Field Descriptions
        10. 6.27.3.9   UART Mode Boot Parameter Table
    28. 6.28 PLL Boot Configuration Settings
    29. 6.29 Second-Level Bootloaders
  7. 7 C66x CorePac
    1. 7.1 Memory Architecture
      1. 7.1.1 L1P Memory
      2. 7.1.2 L1D Memory
      3. 7.1.3 L2 Memory
      4. 7.1.4 MSM SRAM
      5. 7.1.5 L3 Memory
    2. 7.2 Memory Protection
    3. 7.3 Bandwidth Management
    4. 7.4 Power-Down Control
    5. 7.5 C66x CorePac Revision
      1. Table 7-2 CorePac Revision ID Register (MM_REVID) Field Descriptions
    6. 7.6 C66x CorePac Register Descriptions
  8. 8 Device Configuration
    1. 8.1 Device Configuration at Device Reset
    2. 8.2 Peripheral Selection After Device Reset
    3. 8.3 Device State Control Registers
      1. 8.3.1  Device Status Register
        1. Table 8-3 Device Status Register Field Descriptions
      2. 8.3.2  Device Configuration Register
        1. Table 8-4 Device Configuration Register Field Descriptions
      3. 8.3.3  JTAG ID (JTAGID) Register Description
        1. Table 8-5 JTAG ID Register Field Descriptions
      4. 8.3.4  Kicker Mechanism (KICK0 and KICK1) Register
      5. 8.3.5  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        1. Table 8-6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
      6. 8.3.6  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        1. Table 8-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
      7. 8.3.7  Reset Status (RESET_STAT) Register
        1. Table 8-8 Reset Status Register (RESET_STAT) Field Descriptions
      8. 8.3.8  Reset Status Clear (RESET_STAT_CLR) Register
        1. Table 8-9 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions
      9. 8.3.9  Boot Complete (BOOTCOMPLETE) Register
        1. Table 8-10 Boot Complete Register (BOOTCOMPLETE) Field Descriptions
      10. 8.3.10 Power State Control (PWRSTATECTL) Register
        1. Table 8-11 Power State Control Register (PWRSTATECTL) Field Descriptions
      11. 8.3.11 NMI Event Generation to CorePac (NMIGRx) Register
        1. Table 8-12 NMI Generation Register (NMIGRx) Field Descriptions
      12. 8.3.12 IPC Generation (IPCGRx) Registers
        1. Table 8-13 IPC Generation Registers (IPCGRx) Field Descriptions
      13. 8.3.13 IPC Acknowledgement (IPCARx) Registers
        1. Table 8-14 IPC Acknowledgement Registers (IPCARx) Field Descriptions
      14. 8.3.14 IPC Generation Host (IPCGRH) Register
        1. Table 8-15 IPC Generation Registers (IPCGRH) Field Descriptions
      15. 8.3.15 IPC Acknowledgement Host (IPCARH) Register
        1. Table 8-16 IPC Acknowledgement Register (IPCARH) Field Descriptions
      16. 8.3.16 Timer Input Selection Register (TINPSEL)
        1. Table 8-17 Timer Input Selection Field Description (TINPSEL)
      17. 8.3.17 Timer Output Selection Register (TOUTPSEL)
        1. Table 8-18 Timer Output Selection Field Description (TOUTPSEL)
      18. 8.3.18 Reset Mux (RSTMUXx) Register
        1. Table 8-19 Reset Mux Register Field Descriptions
      19. 8.3.19 Device Speed (DEVSPEED) Register
        1. Table 8-20 Device Speed Register Field Descriptions
      20. 8.3.20 Pin Control 0 (PIN_CONTROL_0) Register
        1. Table 8-21 Pin Control 0 Register Field Descriptions
      21. 8.3.21 Pin Control 1 (PIN_CONTROL_1) Register
        1. Table 8-22 Pin Control 1 Register Field Descriptions
      22. 8.3.22 uPP Clock Source (UPP_CLOCK) Register
        1. Table 8-23 uPP Clock Source Register Field Descriptions
    4. 8.4 Pullup and Pulldown Resistors
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix
    3. 9.3 TeraNet Switch Fabric Connections
    4. 9.4 Bus Priorities
      1. 9.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register
        1. Table 9-3 Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
      2. 9.4.2 EMAC / uPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register
        1. Table 9-4 EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) Field Descriptions
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Related Links
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CZH|625
  • GZH|625
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8.1 Interrupt Sources and Interrupt Controller

The CPU interrupts on the C665x device are configured through the C66x CorePac Interrupt Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the 12 CPU interrupt inputs (CPUINT4–CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system events consist of both internally-generated events (within the CorePac) and chip-level events.

Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. In addition, error-class events or infrequently used events are also routed through the system event router to offload the C66x CorePac interrupt selector. This is accomplished through CIC blocks, CIC[2:0]. This is clocked using CPU/6.

The event controllers consist of simple combination logic to provide additional events to the C66x CorePacs, plus the EDMA3_CC and CIC0 provide 12 additional events as well as 8 broadcast events to the C66x CorePacs. CIC1 provides 18 additional events to EDMA3_CC, and CIC2 provides 32 additional events to HyperLink.

There are numerous events on the chip-level. The chip-level CIC provides a flexible way to combine and remap those events. Multiple events can be combined to a single event through chip-level CIC. However, an event can be mapped only to a single event output from the chip-level CIC. The chip-level CIC also allows the software to trigger system events through memory writes. The broadcast events to C66x CorePacs can be used for synchronization among multiple cores, interprocessor communication purposes, and so forth. For more details on the CIC features, see the Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide.

NOTE

Modules such as MPU, Tracer, and BOOT_CFG have level interrupts and an EOI handshaking interface. The EOI value is 0 for MPU, Tracer, and BOOT_CFG.

Figure 6-18 shows the C665x interrupt topology.

TMS320C6655 TMS320C6657 Interrupt_Topology_block_diagram_6655-57.gifFigure 6-18 C665x Interrupt Topology

Table 6-26 shows the mapping of system events. For more information on the Interrupt Controller, see the C66x CorePac User's Guide.

Table 6-26 C665x System Event Inputs — C66x CorePac Primary Interrupts

INPUT EVENT NUMBER INTERRUPT EVENT DESCRIPTION
0 EVT0 Event combiner 0 output
1 EVT1 Event combiner 1 output
2 EVT2 Event combiner 2 output
3 EVT3 Event combiner 3 output
4 TETBHFULLINTn(1) TETB is half full
5 TETBFULLINTn(1) TETB is full
6 TETBACQINTn(1) Acquisition has been completed
7 TETBOVFLINTn(1) Overflow condition interrupt
8 TETBUNFLINTn(1) Underflow condition interrupt
9 EMU_DTDMA ECM interrupt for:
  • 1. Host scan access
  • 2. DTDMA transfer complete
  • 3. AET interrupt
10 MSMC_mpf_errorn(2) Memory protection fault indicators for local core
11 EMU_RTDXRX RTDX receive complete
12 EMU_RTDXTX RTDX transmit complete
13 IDMA0 IDMA channel 0 interrupt
14 IDMA1 IDMA channel 1 interrupt
15 SEMERRn(3) Semaphore error interrupt
16 SEMINTn(3) Semaphore interrupt
17 PCIExpress_MSI_INTn(4) Message signaled interrupt mode
18 PCIExpress_MSI_INTn+4(4) Message signaled interrupt mode
19 MACINTn(9) EMAC interrupt
20 INTDST(n+16)(5) SRIO Interrupt
21 INTDST(n+20)(6) SRIO Interrupt
22 CIC0_OUT(0+20*n)(7) Interrupt Controller Output
23 CIC0_OUT(1+20*n)(7) Interrupt Controller Output
24 CIC0_OUT(2+20*n)(7) Interrupt Controller Output
25 CIC0_OUT(3+20*n)(7) Interrupt Controller Output
26 CIC0_OUT(4+20*n)(7) Interrupt Controller Output
27 CIC0_OUT(5+20*n)(7) Interrupt Controller Output
28 CIC0_OUT(6+20*n)(7) Interrupt Controller Output
29 CIC0_OUT(7+20*n)(7) Interrupt Controller Output
30 CIC0_OUT(8+20*n)(7) Interrupt Controller Output
31 CIC0_OUT(9+20*n)(7) Interrupt Controller Output
32 QM_INT_LOW_0 QM Interrupt for 0~31 Queues
33 QM_INT_LOW_1 QM Interrupt for 32~63 Queues
34 QM_INT_LOW_2 QM Interrupt for 64~95 Queues
35 QM_INT_LOW_3 QM Interrupt for 96~127 Queues
36 QM_INT_LOW_4 QM Interrupt for 128~159 Queues
37 QM_INT_LOW_5 QM Interrupt for 160~191 Queues
38 QM_INT_LOW_6 QM Interrupt for 192~223 Queues
39 QM_INT_LOW_7 QM Interrupt for 224~255 Queues
40 QM_INT_LOW_8 QM Interrupt for 256~287 Queues
41 QM_INT_LOW_9 QM Interrupt for 288~319 Queues
42 QM_INT_LOW_10 QM Interrupt for 320~351 Queues
43 QM_INT_LOW_11 QM Interrupt for 352~383 Queues
44 QM_INT_LOW_12 QM Interrupt for 384~415 Queues
45 QM_INT_LOW_13 QM Interrupt for 416~447 Queues
46 QM_INT_LOW_14 QM Interrupt for 448~479 Queues
47 QM_INT_LOW_15 QM Interrupt for 480~511 Queues
48 QM_INT_HIGH_n(7) QM Interrupt for Queue 704+n(7)
49 QM_INT_HIGH_(n+4)(7) QM Interrupt for Queue 708+n(7)
50 QM_INT_HIGH_(n+8)(7) QM Interrupt for Queue 712+n(7)
51 QM_INT_HIGH_(n+12)(7) QM Interrupt for Queue 716+n(7)
52 QM_INT_HIGH_(n+16)(7) QM Interrupt for Queue 720+n(7)
53 QM_INT_HIGH_(n+20)(7) QM Interrupt for Queue 724+n(7)
54 QM_INT_HIGH_(n+24)(7) QM Interrupt for Queue 728+n(7)
55 QM_INT_HIGH_(n+28)(7) QM Interrupt for Queue 732+n(7)
56 CIC0_OUT40 Interrupt Controller Output
57 CIC0_OUT41 Interrupt Controller Output
58 CIC0_OUT42 Interrupt Controller Output
59 CIC0_OUT43 Interrupt Controller Output
60 CIC0_OUT44 Interrupt Controller Output
61 CIC0_OUT45 Interrupt Controller Output
62 CIC0_OUT46 Interrupt Controller Output
63 CIC0_OUT47 Interrupt Controller Output
64 TINTLn(8) Local timer interrupt low
65 TINTHn(8) Local timer interrupt high
66 TINT2L Timer2 interrupt low
67 TINT2H Timer2 interrupt high
68 TINT3L Timer3 interrupt low
69 TINT3H Timer3 interrupt high
70 PCIExpress_MSI_INTn+2(4) Message signaled interrupt mode
71 PCIExpress_MSI_INTn+6(4) Message signaled interrupt mode
72 GPINT2 GPIO interrupt
73 GPINT3 GPIO interrupt
74 MACINTn+2(9) EMAC interrupt
75 MACTXINTn+2(9) EMAC interrupt
76 MACTRESHn+2(9) EMAC interrupt
77 MACRXINTn+2(9) EMAC interrupt
78 GPINT4 GPIO interrupt
79 GPINT5 GPIO interrupt
80 GPINT6 GPIO interrupt
81 GPINT7 GPIO interrupt
82 GPINT8 GPIO interrupt
83 GPINT9 GPIO interrupt
84 GPINT10 GPIO interrupt
85 GPINT11 GPIO interrupt
86 GPINT12 GPIO interrupt
87 GPINT13 GPIO interrupt
88 GPINT14 GPIO interrupt
89 GPINT15 GPIO interrupt
90 IPC_LOCAL Inter DSP interrupt from IPCGRn
91 GPINTn(10) Local GPIO interrupt
92 CIC0_OUT(10+20*n)(7) Interrupt Controller Output
93 CIC0_OUT(11+20*n)(7) Interrupt Controller Output
94 MACTXINTn(9) EMAC interrupt
95 MACTRESHn(9) EMAC interrupt
96 INTERR Dropped CPU interrupt event
97 EMC_IDMAERR Invalid IDMA parameters
98 Reserved
99 MACRXINTn(9) EMAC interrupt
100 EFIINTA EFI Interrupt from side A
101 EFIINTB EFI Interrupt from side B
102 QM_INT_HIGH_(n+2)(7) QM Interrupt for Queue 706+n(7)
103 QM_INT_HIGH_(n+6)(7) QM Interrupt for Queue 710+n(7)
104 QM_INT_HIGH_(n+10)(7) QM Interrupt for Queue 714+n(7)
105 QM_INT_HIGH_(n+14)(7) QM Interrupt for Queue 718+n(7)
106 QM_INT_HIGH_(n+18)(7) QM Interrupt for Queue 722+n(7)
107 QM_INT_HIGH_(n+22)(7) QM Interrupt for Queue 726+n(7)
108 QM_INT_HIGH_(n+26)(7) QM Interrupt for Queue 730+n(7)
109 QM_INT_HIGH_(n+30)(7) QM Interrupt for Queue 734+n(7)
110 MDMAERREVT VbusM error event
111 Reserved
112 INTDST(n+18)(11) SRIO Interrupt
113 PMC_ED Single bit error detected during DMA read
114 INTDST(n+22)(12) SRIO Interrupt
115 EDMA3_CC_AETEVT EDMA3 CC AET Event
116 UMC_ED1 Corrected bit error detected
117 UMC_ED2 Uncorrected bit error detected
118 PDC_INT Power down sleep interrupt
119 SYS_CMPA SYS CPU memory protection fault event
120 PMC_CMPA PMC CPU memory protection fault event
121 PMC_DMPA PMC DMA memory protection fault event
122 DMC_CMPA DMC CPU memory protection fault event
123 DMC_DMPA DMC DMA memory protection fault event
124 UMC_CMPA UMC CPU memory protection fault event
125 UMC_DMPA UMC DMA memory protection fault event
126 EMC_CMPA EMC CPU memory protection fault event
127 EMC_BUSERR EMC bus error interrupt
(1) CorePac[n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn, and TETBUNFLINTn.
(2) CorePac[n] will receive MSMC_mpf_errorn.
(3) CorePac[n] will receive SEMINTn and SEMERRn.
(4) CorePac[n] will receive PCIEXpress_MSI_INTn.
(5) CorePac[n] will receive INTDST(n+16).
(6) CorePac[n] will receive INTDST(n+20).
(7) n is core number.
(8) CorePac[n] will receive TINTLn and TINTHn.
(9) CorePac[n] will receive MACINTn/MACRXINTn/MACTXINTn/MACTRESHn.
(10) CorePac[n] will receive GPINTn.
(11) CorePac[n] will receive INTDST(n+18).
(12) CorePac[n] will receive INTDST(n+22).

Table 6-27 CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs)

INPUT EVENT NO. ON CIC SYSTEM INTERRUPT DESCRIPTION
0 GPINT16 GPIO interrupt
1 GPINT17 GPIO interrupt
2 GPINT18 GPIO interrupt
3 GPINT19 GPIO interrupt
4 GPINT20 GPIO interrupt
5 GPINT21 GPIO interrupt
6 GPINT22 GPIO interrupt
7 GPINT23 GPIO interrupt
8 GPINT24 GPIO interrupt
9 GPINT25 GPIO interrupt
10 GPINT26 GPIO interrupt
11 GPINT27 GPIO interrupt
12 GPINT28 GPIO interrupt
13 GPINT29 GPIO interrupt
14 GPINT30 GPIO interrupt
15 GPINT31 GPIO interrupt
16 EDMA3_CC_ERRINT EDMA3_CC error interrupt
17 EDMA3_CC_MPINT EDMA3_CC memory protection interrupt
18 EDMA3_TC_ERRINT0 EDMA3_CC TC0 error interrupt
19 EDMA3_TC_ERRINT1 EDMA3_CC TC1 error interrupt
20 EDMA3_TC_ERRINT2 EDMA3_CC TC2 error interrupt
21 EDMA3_TC_ERRINT3 EDMA3_CC TC3 error interrupt
22 EDMA3_CC_GINT EDMA3_CC GINT
23 Reserved
24 EDMA3_CC_INT0 EDMA3_CC individual completion interrupt
25 EDMA3_CC_INT1 EDMA3_CC individual completion interrupt
26 EDMA3_CC_INT2 EDMA3_CC individual completion interrupt
27 EDMA3_CC_INT3 EDMA3_CC individual completion interrupt
28 EDMA3_CC_INT4 EDMA3_CC individual completion interrupt
29 EDMA3_CC_INT5 EDMA3_CC individual completion interrupt
30 EDMA3_CC_INT6 EDMA3_CC individual completion interrupt
31 EDMA3_CC_INT7 EDMA3_CC individual completion interrupt
32 MCBSP0_RINT McBSP0 interrupt
33 MCBSP0_XINT McBSP0 interrupt
34 MCBSP0_REVT McBSP0 interrupt
35 MCBSP0_XEVT McBSP0 interrupt
36 MCBSP1_RINT McBSP1 interrupt
37 MCBSP1_XINT McBSP1 interrupt
38 MCBSP1_REVT McBSP1 interrupt
39 MCBSP1_XEVT McBSP1 interrupt
40 UARTINT_B UART_1 interrupt
41 URXEVT_B UART_1 interrupt
42 UTXEVT_B UART_1 interrupt
43 Reserved
44 Reserved
45 Reserved
46 Reserved
47 Reserved
48 PCIEXpress_ERR_INT Protocol error interrupt
49 PCIEXpress_PM_INT Power management interrupt
50 PCIEXpress_Legacy_INTA Legacy interrupt mode
51 PCIEXpress_Legacy_INTB Legacy interrupt mode
52 PCIEXpress_Legacy_CIC Legacy interrupt mode
53 PCIEXpress_Legacy_INTD Legacy interrupt mode
54 SPIINT0 SPI interrupt0
55 SPIINT1 SPI interrupt1
56 SPIXEVT Transmit event
57 SPIREVT Receive event
58 I2CINT I2C interrupt
59 I2CREVT I2C receive event
60 I2CXEVT I2C transmit event
61 Reserved
62 Reserved
63 TETBHFULLINT TETB is half full
64 TETBFULLINT TETB is full
65 TETBACQINT Acquisition has been completed
66 TETBOVFLINT Overflow condition occur
67 TETBUNFLINT Underflow condition occur
68 SEMINT2 Semaphore interrupt
69 SEMINT3 Semaphore interrupt
70 SEMERR2 Semaphore interrupt
71 SEMERR3 Semaphore interrupt
72 Reserved
73 Tracer_core_0_INTD Tracer sliding time window interrupt for individual core
74 Tracer_core_1_INTD Tracer sliding time window interrupt for individual core (C6657 only)
75 Reserved
76 Reserved
77 Tracer_DDR_INTD Tracer sliding time window interrupt for DDR3 EMIF1
78 Tracer_MSMC_0_INTD Tracer sliding time window interrupt for MSMC SRAM bank0
79 Tracer_MSMC_1_INTD Tracer sliding time window interrupt for MSMC SRAM bank1
80 Tracer_MSMC_2_INTD Tracer sliding time window interrupt for MSMC SRAM bank2
81 Tracer_MSMC_3_INTD Tracer sliding time window interrupt for MSMC SRAM bank3
81 Tracer_CFG_INTD Tracer sliding time window interrupt for CFG0 TeraNet
82 Tracer_QM_CFG_INTD Tracer sliding time window interrupt for QM_SS CFG
84 Tracer_QM_DMA_INTD Tracer sliding time window interrupt for QM_SS slave
85 Tracer_SM_INTD Tracer sliding time window interrupt for semaphore
86 PSC_ALLINT Power/sleep controller interrupt
87 MSMC_scrub_cerror Correctable (1-bit) soft error detected during scrub cycle
88 BOOTCFG_INTD Chip-level MMR error register
89 po_vcon_smpserr_intr SmartReflex VolCon error status
90 MPU0_INTD (MPU0_ADDR_ERR_INT and MPU0_PROT_ERR_INT combined) MPU0 addressing violation interrupt and protection violation interrupt.
91 Reserved
92 MPU1_INTD (MPU1_ADDR_ERR_INT and MPU1_PROT_ERR_INT combined) MPU1 addressing violation interrupt and protection violation interrupt.
93 Reserved
94 MPU2_INTD (MPU2_ADDR_ERR_INT and MPU2_PROT_ERR_INT combined) MPU2 addressing violation interrupt and protection violation interrupt.
95 Reserved
96 MPU3_INTD (MPU3_ADDR_ERR_INT and MPU3_PROT_ERR_INT combined) MPU3 addressing violation interrupt and protection violation interrupt.
97 Reserved
98 MSMC_dedc_cerror Correctable (1-bit) soft error detected on SRAM read
99 MSMC_dedc_nc_error Noncorrectable (2-bit) soft error detected on SRAM read
100 MSMC_scrub_nc_error Noncorrectable (2-bit) soft error detected during scrub cycle
101 Reserved
102 MSMC_mpf_error8 Memory protection fault indicators for each system master PrivID
103 MSMC_mpf_error9 Memory protection fault indicators for each system master PrivID
104 MSMC_mpf_error10 Memory protection fault indicators for each system master PrivID
105 MSMC_mpf_error11 Memory protection fault indicators for each system master PrivID
105 MSMC_mpf_error12 Memory protection fault indicators for each system master PrivID
107 MSMC_mpf_error13 Memory protection fault indicators for each system master PrivID
108 MSMC_mpf_error14 Memory protection fault indicators for each system master PrivID
109 MSMC_mpf_error15 Memory protection fault indicators for each system master PrivID
110 DDR3_ERR DDR3 EMIF error interrupt
111 HyperLink_int_o HyperLink interrupt
112 INTDST0 RapidIO interrupt
113 INTDST1 RapidIO interrupt
114 INTDST2 RapidIO interrupt
115 INTDST3 RapidIO interrupt
116 INTDST4 RapidIO interrupt
117 INTDST5 RapidIO interrupt
118 INTDST6 RapidIO interrupt
119 INTDST7 RapidIO interrupt
120 INTDST8 RapidIO interrupt
121 INTDST9 RapidIO interrupt
122 INTDST10 RapidIO interrupt
123 INTDST11 RapidIO interrupt
124 INTDST12 RapidIO interrupt
125 INTDST13 RapidIO interrupt
126 INTDST14 RapidIO interrupt
127 INTDST15 RapidIO interrupt
128 Reserved
129 Reserved
130 po_vp_smpsack_intr Indicating that Volt_Proc receives the r-edge at its smpsack input
131 Reserved
132 Reserved
133 Reserved
134 QM_INT_PASS_TXQ_PEND_662 Queue manager pend event
135 QM_INT_PASS_TXQ_PEND_663 Queue manager pend event
136 QM_INT_PASS_TXQ_PEND_664 Queue manager pend event
137 QM_INT_PASS_TXQ_PEND_665 Queue manager pend event
138 QM_INT_PASS_TXQ_PEND_666 Queue manager pend event
139 QM_INT_PASS_TXQ_PEND_667 Queue manager pend event
140 QM_INT_PASS_TXQ_PEND_668 Queue manager pend event
141 QM_INT_PASS_TXQ_PEND_669 Queue manager pend event
142 QM_INT_PASS_TXQ_PEND_670 Queue manager pend event
143 VCP0INT VCP2_0 interrupt
144 VCP1INT VCP2_1 interrupt
145 TINT4L Timer4 interrupt low
146 TINT4H Timer4 interrupt high
147 VCPAREVT VCP2_A receive event
148 VCPAXEVT VCP2_A transmit event
149 VCPBREVT VCP2_B receive event
150 VCPBXEVT VCP2_B transmit event
151 TINT5L Timer5 interrupt low
152 TINT5H Timer5 interrupt high
153 TINT6L Timer6 interrupt low
154 TINT6H Timer6 interrupt high
155 TCP_INTD TCP3d interrupt
156 UPPINT uPP interrupt
157 TCP_REVT0 TCP3d interrupt
158 TCP_XEVT0 TCP3d interrupt
159 Reserved
160 MSMC_mpf_error2 Memory protection fault indicators for each system master PrivID
161 MSMC_mpf_error3 Memory protection fault indicators for each system master PrivID
162 TINT7L Timer7 interrupt low
163 TINT7H Timer7interrupt high
164 UARTINT_A UART_0 interrupt
165 URXEVT_A UART_0 interrupt
166 UTXEVT_A UART_0 interrupt
167 EASYNCERR EMIF16 error interrupt
168 Tracer_EMIF16 Tracer sliding time window interrupt for EMIF16
169 Reserved
170 MSMC_mpf_error4 Memory protection fault indicators for each system master PrivID
171 MSMC_mpf_error5 Memory protection fault indicators for each system master PrivID
172 MSMC_mpf_error6 Memory protection fault indicators for each system master PrivID
173 MSMC_mpf_error7 Memory protection fault indicators for each system master PrivID
174 MPU4_INTD (MPU4_ADDR_ERR_INT and MPU4_PROT_ERR_INT combined) MPU4 addressing violation interrupt and protection violation interrupt.
175 QM_INT_PASS_TXQ_PEND_671 Queue manager pend event
176 QM_INT_PKTDMA_0 QM interrupt for CDMA starvation
177 QM_INT_PKTDMA_1 QM interrupt for CDMA starvation
178 SRIO_INT_PKTDMA_0 SRIO interrupt for CDMA starvation
179 Reserved
180 Reserved
181 SmartReflex_intrreq0 SmartReflex sensor interrupt
182 SmartReflex_intrreq1 SmartReflex sensor interrupt
183 SmartReflex_intrreq2 SmartReflex sensor interrupt
184 SmartReflex_intrreq3 SmartReflex sensor interrupt
185 VPNoSMPSAck VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval
186 VPEqValue SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage
187 VPMaxVdd The new voltage required is equal to or greater than MaxVdd.
188 VPMinVdd The new voltage required is equal to or less than MinVdd.
189 VPINIDLE Indicating that the FSM of voltage processor is in idle.
190 VPOPPChangeDone Indicating that the average frequency error is within the desired limit.
191 Reserved
192 MACINT4 EMAC interrupt
193 MACRXINT4 EMAC interrupt
194 MACTXINT4 EMAC interrupt
195 MACTRESH4 EMAC interrupt
196 MACINT5 EMAC interrupt
197 MACRXINT5 EMAC interrupt
198 MACTXINT5 EMAC interrupt
199 MACTRESH5 EMAC interrupt
200 MACINT6 EMAC interrupt
201 MACRXINT6 EMAC interrupt
202 MACTXINT6 EMAC interrupt
203 MACTRESH6 EMAC interrupt
204 MACINT7 EMAC interrupt
205 MACRXINT7 EMAC interrupt
206 MACTXINT7 EMAC interrupt
207 MACTRESH7 EMAC interrupt

Table 6-28 CIC1 Event Inputs (Secondary Events for EDMA3_CC)

INPUT EVENT NO. ON CIC SYSTEM INTERRUPT DESCRIPTION
0 GPINT8 GPIO interrupt
1 GPINT9 GPIO interrupt
2 GPINT10 GPIO interrupt
3 GPINT11 GPIO interrupt
4 GPINT12 GPIO interrupt
5 GPINT13 GPIO interrupt
6 GPINT14 GPIO interrupt
7 GPINT15 GPIO interrupt
8 Reserved
9 Reserved
10 TETBACQINT System TETB acquisition has been completed
11 Reserved
12 Reserved
13 TETBACQINT0 TETB0 acquisition has been completed
14 Reserved
15 Reserved
16 TETBACQINT1 TETB1 acquisition has been completed (C6657 only)
17 GPINT16 GPIO interrupt
18 GPINT17 GPIO interrupt
19 GPINT18 GPIO interrupt
20 GPINT19 GPIO interrupt
21 GPINT20 GPIO interrupt
22 GPINT21 GPIO interrupt
23 Reserved
24 QM_INT_HIGH_16 QM interrupt
25 QM_INT_HIGH_17 QM interrupt
26 QM_INT_HIGH_18 QM interrupt
27 QM_INT_HIGH_19 QM interrupt
28 QM_INT_HIGH_20 QM interrupt
29 QM_INT_HIGH_21 QM interrupt
30 QM_INT_HIGH_22 QM interrupt
31 QM_INT_HIGH_23 QM interrupt
32 QM_INT_HIGH_24 QM interrupt
33 QM_INT_HIGH_25 QM interrupt
34 QM_INT_HIGH_26 QM interrupt
35 QM_INT_HIGH_27 QM interrupt
36 QM_INT_HIGH_28 QM interrupt
37 QM_INT_HIGH_29 QM interrupt
38 QM_INT_HIGH_30 QM interrupt
39 QM_INT_HIGH_31 QM interrupt
40 Reserved
41 Reserved
42 Reserved
43 Reserved
44 Reserved
45 Tracer_core_0_INTD Tracer sliding time window interrupt for individual core
46 Tracer_core_1_INTD Tracer sliding time window interrupt for individual core (C6657 only)
47 GPINT22 GPIO interrupt
48 GPINT23 GPIO interrupt
49 Tracer_DDR_INTD Tracer sliding time window interrupt for DDR3 EMIF
50 Tracer_MSMC_0_INTD Tracer sliding time window interrupt for MSMC SRAM bank0
51 Tracer_MSMC_1_INTD Tracer sliding time window interrupt for MSMC SRAM bank1
52 Tracer_MSMC_2_INTD Tracer sliding time window interrupt for MSMC SRAM bank2
53 Tracer_MSMC_3_INTD Tracer sliding time window interrupt for MSMC SRAM bank3
54 Tracer_CFG_INTD Tracer sliding time window interrupt for CFG0 TeraNet
55 Tracer_QM_CFG_INTD Tracer sliding time window interrupt for QM_SS CFG
56 Tracer_QM_DMA_INTD Tracer sliding time window interrupt for QM_SS slave port
57 Tracer_SEM_INTD Tracer sliding time window interrupt for semaphore
58 SEMERR0 Semaphore interrupt
59 SEMERR1 Semaphore interrupt
60 SEMERR2 Semaphore interrupt
61 SEMERR3 Semaphore interrupt
62 BOOTCFG_INTD BOOTCFG interrupt BOOTCFG_ERR and BOOTCFG_PROT
63 UPPINT uPP interrupt
64 MPU0_INTD (MPU0_ADDR_ERR_INT and MPU0_PROT_ERR_INT combined) MPU0 addressing violation interrupt and protection violation interrupt.
65 MSMC_scrub_cerror Correctable (1-bit) soft error detected during scrub cycle
66 MPU1_INTD (MPU1_ADDR_ERR_INT and MPU1_PROT_ERR_INT combined) MPU1 addressing violation interrupt and protection violation interrupt.
67 RapidIO_INT_PKTDMA_0 RapidIO interrupt for packet DMA starvation
68 MPU2_INTD (MPU2_ADDR_ERR_INT and MPU2_PROT_ERR_INT combined) MPU2 addressing violation interrupt and protection violation interrupt.
69 QM_INT_PKTDMA_0 QM interrupt for packet DMA starvation
70 MPU3_INTD (MPU3_ADDR_ERR_INT and MPU3_PROT_ERR_INT combined) MPU3 addressing violation interrupt and protection violation interrupt.
71 QM_INT_PKTDMA_1 QM interrupt for packet DMA starvation
72 MSMC_dedc_cerror Correctable (1-bit) soft error detected on SRAM read
73 MSMC_dedc_nc_error Noncorrectable (2-bit) soft error detected on SRAM read
74 MSMC_scrub_nc_error Noncorrectable (2-bit) soft error detected during scrub cycle
75 Reserved
76 MSMC_mpf_error0 Memory protection fault indicators for each system master PrivID
77 MSMC_mpf_error1 Memory protection fault indicators for each system master PrivID
78 MSMC_mpf_error2 Memory protection fault indicators for each system master PrivID
79 MSMC_mpf_error3 Memory protection fault indicators for each system master PrivID
80 MSMC_mpf_error4 Memory protection fault indicators for each system master PrivID
81 MSMC_mpf_error5 Memory protection fault indicators for each system master PrivID
82 MSMC_mpf_error6 Memory protection fault indicators for each system master PrivID
83 MSMC_mpf_error7 Memory protection fault indicators for each system master PrivID
84 MSMC_mpf_error8 Memory protection fault indicators for each system master PrivID
85 MSMC_mpf_error9 Memory protection fault indicators for each system master PrivID
86 MSMC_mpf_error10 Memory protection fault indicators for each system master PrivID
87 MSMC_mpf_error11 Memory protection fault indicators for each system master PrivID
88 MSMC_mpf_error12 Memory protection fault indicators for each system master PrivID
89 MSMC_mpf_error13 Memory protection fault indicators for each system master PrivID
90 MSMC_mpf_error14 Memory protection fault indicators for each system master PrivID
91 MSMC_mpf_error15 Memory protection fault indicators for each system master PrivID
92 Reserved
93 INTDST0 RapidIO interrupt
94 INTDST1 RapidIO interrupt
95 INTDST2 RapidIO interrupt
96 INTDST3 RapidIO interrupt
97 INTDST4 RapidIO interrupt
98 INTDST5 RapidIO interrupt
99 INTDST6 RapidIO interrupt
100 INTDST7 RapidIO interrupt
101 INTDST8 RapidIO interrupt
102 INTDST9 RapidIO interrupt
103 INTDST10 RapidIO interrupt
104 INTDST11 RapidIO interrupt
105 INTDST12 RapidIO interrupt
106 INTDST13 RapidIO interrupt
107 INTDST14 RapidIO interrupt
108 INTDST15 RapidIO interrupt
109 INTDST16 RapidIO interrupt
110 INTDST17 RapidIO interrupt
111 INTDST18 RapidIO interrupt
112 INTDST19 RapidIO interrupt
113 INTDST20 RapidIO interrupt
114 INTDST21 RapidIO interrupt
115 INTDST22 RapidIO interrupt
116 INTDST23 RapidIO interrupt
117 GPINT24 GPIO interrupt
118 GPINT25 GPIO interrupt
119 VCPAINT VCP2_A interrupt
120 VCPBINT VCP2_B interrupt
121 GPINT26 GPIO interrupt
122 GPINT27 GPIO interrupt
123 TCP3D_INTD Error interrupt TCP3DINT0 and TCP3DINT1
124 GPINT28 GPIO interrupt
125 GPINT29 GPIO interrupt
126 GPINT30 GPIO interrupt
127 GPINT31 GPIO interrupt
128 GPINT4 GPIO interrupt
129 GPINT5 GPIO interrupt
130 GPINT6 GPIO interrupt
131 GPINT7 GPIO interrupt
132 Hyperlink_int_o Hyperlink interrupt
133 Tracer_EMIF16 Tracer sliding time window interrupt for EMIF16
134 EASYNCERR EMIF16 error interrupt
135 MPU4_INTD (MPU4_ADDR_ERR_INT and MPU4_PROT_ERR_INT combined) MPU4 addressing violation interrupt and protection violation interrupt.
136 Reserved
137 QM_INT_HIGH_0 QM interrupt
138 QM_INT_HIGH_1 QM interrupt
139 QM_INT_HIGH_2 QM interrupt
140 QM_INT_HIGH_3 QM interrupt
141 QM_INT_HIGH_4 QM interrupt
142 QM_INT_HIGH_5 QM interrupt
143 QM_INT_HIGH_6 QM interrupt
144 QM_INT_HIGH_7 QM interrupt
145 QM_INT_HIGH_8 QM interrupt
146 QM_INT_HIGH_9 QM interrupt
147 QM_INT_HIGH_10 QM interrupt
148 QM_INT_HIGH_11 QM interrupt
149 QM_INT_HIGH_12 QM interrupt
150 QM_INT_HIGH_13 QM interrupt
151 QM_INT_HIGH_14 QM interrupt
152 QM_INT_HIGH_15 QM interrupt
153 Reserved
154 Reserved
155 Reserved
156 Reserved
157 Reserved
158 Reserved
159 DDR3_ERR DDR3 error interrupt

Table 6-29 CIC2 Event Inputs (Secondary Events for HyperLink)

INPUT EVENT NO. ON CIC SYSTEM INTERRUPT DESCRIPTION
0 GPINT0 GPIO interrupt
1 GPINT1 GPIO interrupt
2 GPINT2 GPIO interrupt
3 GPINT3 GPIO interrupt
4 GPINT4 GPIO interrupt
5 GPINT5 GPIO interrupt
6 GPINT6 GPIO interrupt
7 GPINT7 GPIO interrupt
8 GPINT8 GPIO interrupt
9 GPINT9 GPIO interrupt
10 GPINT10 GPIO interrupt
11 GPINT11 GPIO interrupt
12 GPINT12 GPIO interrupt
13 GPINT13 GPIO interrupt
14 GPINT14 GPIO interrupt
15 GPINT15 GPIO interrupt
16 TETBHFULLINT System TETB is half full
17 TETBFULLINT System TETB is full
18 TETBACQINT System TETB acquisition has been completed
19 TETBHFULLINT0 TETB0 is half full
20 TETBFULLINT0 TETB0 is full
21 TETBACQINT0 TETB0 acquisition has been completed
22 TETBHFULLINT1 TETB1 is half full
23 TETBFULLINT1 TETB1 is full
24 TETBACQINT1 TETB1 acquisition has been completed
25 GPINT16 GPIO interrupt
26 GPINT17 GPIO interrupt
27 GPINT18 GPIO interrupt
28 GPINT19 GPIO interrupt
29 GPINT20 GPIO interrupt
30 GPINT21 GPIO interrupt
31 Tracer_core_0_INTD Tracer sliding time window interrupt for individual core
32 Tracer_core_1_INTD Tracer sliding time window interrupt for individual core (C6657 only)
33 GPINT22 GPIO interrupt
34 GPINT23 GPIO interrupt
35 Tracer_DDR_INTD Tracer sliding time window interrupt for DDR3 EMIF1
36 Tracer_MSMC_0_INTD Tracer sliding time window interrupt for MSMC SRAM bank0
37 Tracer_MSMC_1_INTD Tracer sliding time window interrupt for MSMC SRAM bank1
38 Tracer_MSMC_2_INTD Tracer sliding time window interrupt for MSMC SRAM bank2
39 Tracer_MSMC_3_INTD Tracer sliding time window interrupt for MSMC SRAM bank3
40 Tracer_CFG_INTD Tracer sliding time window interrupt for CFG0 TeraNet
41 Tracer_QM_SS_CFG_INTD Tracer sliding time window interrupt for QM_SS CFG
42 Tracer_QM_SS_DMA_INTD Tracer sliding time window interrupt for QM_SS slave port
43 Tracer_SEM_INTD Tracer sliding time window interrupt for semaphore
44 Reserved
45 GPINT24 GPIO interrupt
46 GPINT25 GPIO interrupt
47 GPINT26 GPIO interrupt
48 GPINT27 GPIO interrupt
49 TINT4L Timer64_4 interrupt low
50 TINT4H Timer64_4 interrupt high
51 TINT5L Timer64_5 interrupt low
52 TINT5H timer64_5 interrupt high
53 TINT6L Timer64_6 interrupt low
54 TINT6H Timer64_6 interrupt high
55 TINT7L Timer64_7 interrupt low
56 TINT7H Timer64_7 interrupt high
57 Reserved
58 Reserved
59 Reserved
60 Tracer_EMIF16 Tracer sliding time window interrupt for TNet_6P_A
61 DDR3_ERR DDR3 EMIF Error interrupt
62 Reserved
63 EASYNCERR EMIF16 error interrupt
64 GPINT28 GPIO interrupt
65 GPINT29 GPIO interrupt
66 GPINT30 GPIO interrupt
67 GPINT31 GPIO interrupt
68 TINT2L Timer2 interrupt low
69 TINT2H Timer2 interrupt high
70 TINT3L Timer2 interrupt low
71 TINT3H Timer2 interrupt high
72-79 Reserved