SPRS814D March   2012  – October 2019 TMS320C6655 , TMS320C6657

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Device Comparison
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Terminal Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for [CZH/GZH] Package
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  SmartReflex
        1. Table 5-1 SmartReflex 4-Pin VID Interface Switching Characteristics
      2. 5.7.2  Reset Electrical Data / Timing
        1. Table 5-2 Reset Timing Requirements
        2. Table 5-3 Reset Switching Characteristics Over Recommended Operating Conditions
        3. Table 5-4 Boot Configuration Timing Requirements
      3. 5.7.3  Main PLL Stabilization, Lock, and Reset Times
      4. 5.7.4  Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
        1. Table 5-6 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements
      5. 5.7.5  DDR3 PLL Input Clock Electrical Data/Timing
        1. Table 5-7 DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
      6. 5.7.6  External Interrupts Electrical Data/Timing
        1. Table 5-8 NMI and Local Reset Timing Requirements
      7. 5.7.7  DDR3 Memory Controller Electrical Data/Timing
      8. 5.7.8  I2C Electrical Data/Timing
        1. 5.7.8.1 Inter-Integrated Circuits (I2C) Timing
          1. Table 5-9  I2C Timing Requirements
          2. Table 5-10 I2C Switching Characteristics
      9. 5.7.9  SPI Peripheral
        1. 5.7.9.1 SPI Timing
          1. Table 5-11 SPI Timing Requirements
          2. Table 5-12 SPI Switching Characteristics
      10. 5.7.10 HyperLink Electrical Data/Timing
        1. Table 5-13 HyperLink Peripheral Timing Requirements
        2. Table 5-14 HyperLink Peripheral Switching Characteristics
      11. 5.7.11 UART Peripheral
        1. Table 5-15 UART Timing Requirements
        2. Table 5-16 UART Switching Characteristics
      12. 5.7.12 EMIF16 Peripheral
        1. 5.7.12.1 EMIF16 Electrical Data/Timing
          1. Table 5-17 EMIF16 Asynchronous Memory Timing Requirements
      13. 5.7.13 MDIO Timing
        1. Table 5-18 MDIO Timing Requirements
        2. Table 5-19 MDIO Switching Characteristics
      14. 5.7.14 Timers Electrical Data/Timing
        1. Table 5-20 Timer Input Timing Requirements
        2. Table 5-21 Timer Output Switching Characteristics
      15. 5.7.15 General-Purpose Input/Output (GPIO)
        1. 5.7.15.1 GPIO Device-Specific Information
        2. 5.7.15.2 GPIO Electrical Data/Timing
          1. Table 5-22 GPIO Input Timing Requirements
          2. Table 5-23 GPIO Output Switching Characteristics
      16. 5.7.16 McBSP Electrical Data/Timing
        1. 5.7.16.1 McBSP Timing
          1. Table 5-24 McBSP Timing Requirements
          2. Table 5-25 McBSP Switching Characteristics
          3. Table 5-26 McBSP Timing Requirements for FSR When GSYNC = 1
      17. 5.7.17 uPP Timing and Switching
        1. Table 5-27 uPP Timing Requirements
        2. Table 5-28 uPP Switching Characteristics
      18. 5.7.18 Trace Electrical Data/Timing
        1. Table 5-29 DSP Trace Switching Characteristics
        2. Table 5-30 STM Trace Switching Characteristics
      19. 5.7.19 JTAG Electrical Data/Timing
        1. Table 5-31 JTAG Test Port Timing Requirements
        2. Table 5-32 JTAG Test Port Switching Characteristics
  6. 6 Detailed Description
    1. 6.1  Recommended Clock and Control Signal Transition Behavior
    2. 6.2  Power Supplies
      1. 6.2.1 Power Supply to Peripheral I/O Mapping
      2. 6.2.2 Power-Supply Sequencing
        1. 6.2.2.1 Core-Before-IO Power Sequencing
        2. 6.2.2.2 IO-Before-Core Power Sequencing
        3. 6.2.2.3 Prolonged Resets
        4. 6.2.2.4 Clocking During Power Sequencing
      3. 6.2.3 Power-Down Sequence
      4. 6.2.4 Power Supply Decoupling and Bulk Capacitors
    3. 6.3  Power Sleep Controller (PSC)
      1. 6.3.1 Power Domains
      2. 6.3.2 Clock Domains
      3. 6.3.3 PSC Register Memory Map
    4. 6.4  Reset Controller
      1. 6.4.1 Power-on Reset
      2. 6.4.2 Hard Reset
      3. 6.4.3 Soft Reset
      4. 6.4.4 Local Reset
      5. 6.4.5 Reset Priority
      6. 6.4.6 Reset Controller Register
    5. 6.5  Main PLL and PLL Controller
      1. 6.5.1 Main PLL Controller Device-Specific Information
        1. 6.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 6.5.1.2 Main PLL Controller Operating Modes
      2. 6.5.2 PLL Controller Memory Map
        1. 6.5.2.1 PLL Secondary Control Register (SECCTL)
          1. Table 6-10 PLL Secondary Control Register (SECCTL) Field Descriptions
        2. 6.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
          1. Table 6-11 PLL Controller Divider Register (PLLDIVn) Field Descriptions
        3. 6.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
          1. Table 6-12 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
        4. 6.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
          1. Table 6-13 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
        5. 6.5.2.5 SYSCLK Status Register (SYSTAT)
          1. Table 6-14 SYSCLK Status Register (SYSTAT) Field Descriptions
        6. 6.5.2.6 Reset Type Status Register (RSTYPE)
          1. Table 6-15 Reset Type Status Register (RSTYPE) Field Descriptions
        7. 6.5.2.7 Reset Control Register (RSTCTRL)
          1. Table 6-16 Reset Control Register (RSTCTRL) Field Descriptions
        8. 6.5.2.8 Reset Configuration Register (RSTCFG)
          1. Table 6-17 Reset Configuration Register (RSTCFG) Field Descriptions
        9. 6.5.2.9 Reset Isolation Register (RSISO)
          1. Table 6-18 Reset Isolation Register (RSISO) Field Descriptions
      3. 6.5.3 Main PLL Control Register
        1. Table 6-19 Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
        2. Table 6-20 Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
      4. 6.5.4 Main PLL and PLL Controller Initialization Sequence
    6. 6.6  DDR3 PLL
      1. 6.6.1 DDR3 PLL Control Register
        1. Table 6-21 DDR3 PLL Control Register 0 Field Descriptions
        2. Table 6-22 DDR3 PLL Control Register 1 Field Descriptions
      2. 6.6.2 DDR3 PLL Device-Specific Information
      3. 6.6.3 DDR3 PLL Initialization Sequence
    7. 6.7  Enhanced Direct Memory Access (EDMA3) Controller
      1. 6.7.1 EDMA3 Device-Specific Information
      2. 6.7.2 EDMA3 Channel Controller Configuration
      3. 6.7.3 EDMA3 Transfer Controller Configuration
      4. 6.7.4 EDMA3 Channel Synchronization Events
    8. 6.8  Interrupts
      1. 6.8.1 Interrupt Sources and Interrupt Controller
      2. 6.8.2 CIC Registers
        1. 6.8.2.1 CIC0 Register Map
        2. 6.8.2.2 CIC1 Register Map
        3. 6.8.2.3 CIC2 Register Map
      3. 6.8.3 Interprocessor Register Map
      4. 6.8.4 NMI and LRESET
    9. 6.9  Memory Protection Unit (MPU)
      1. 6.9.1 MPU Registers
        1. 6.9.1.1 MPU Register Map
        2. 6.9.1.2 Device-Specific MPU Registers
          1. 6.9.1.2.1 Configuration Register (CONFIG)
            1. Table 6-44 Configuration Register (CONFIG) Field Descriptions
      2. 6.9.2 MPU Programmable Range Registers
        1. 6.9.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
          1. Table 6-45 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions
        2. 6.9.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
          1. Table 6-46 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions
        3. 6.9.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
          1. Table 6-47 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
        4. 6.9.2.4 MPU Registers Reset Values
    10. 6.10 DDR3 Memory Controller
      1. 6.10.1 DDR3 Memory Controller Device-Specific Information
    11. 6.11 I2C Peripheral
      1. 6.11.1 I2C Device-Specific Information
      2. 6.11.2 I2C Peripheral Register Description(s)
    12. 6.12 HyperLink Peripheral
      1. 6.12.1 HyperLink Device-Specific Interrupt Event
    13. 6.13 PCIe Peripheral
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Device-Specific Information
      2. 6.14.2 EMAC Peripheral Register Description(s)
      3. 6.14.3 EMAC Electrical Data/Timing (SGMII)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Peripheral Registers
    16. 6.16 Timers
      1. 6.16.1 Timers Device-Specific Information
    17. 6.17 Semaphore2
    18. 6.18 Multichannel Buffered Serial Port (McBSP)
      1. 6.18.1 McBSP Peripheral Register
    19. 6.19 Universal Parallel Port (uPP)
      1. 6.19.1 uPP Register Descriptions
    20. 6.20 Serial RapidIO (SRIO) Port
    21. 6.21 Turbo Decoder Coprocessor (TCP3d)
    22. 6.22 Enhanced Viterbi-Decoder Coprocessor (VCP2)
    23. 6.23 Emulation Features and Capability
      1. 6.23.1 Advanced Event Triggering (AET)
      2. 6.23.2 Trace
      3. 6.23.3 IEEE 1149.1 JTAG
        1. 6.23.3.1 IEEE 1149.1 JTAG Compatibility Statement
    24. 6.24 DSP Core Description
    25. 6.25 Memory Map Summary
    26. 6.26 Boot Sequence
    27. 6.27 Boot Modes Supported and PLL Settings
      1. 6.27.1 Boot Device Field
        1. Table 6-64 Boot Mode Pins: Boot Device Values
      2. 6.27.2 Device Configuration Field
        1. 6.27.2.1 EMIF16 / UART / No Boot Device Configuration
          1. Table 6-65 EMIF16 / UART / No Boot Configuration Field Descriptions
          2. 6.27.2.1.1 No Boot Mode
            1. Table 6-66 No Boot Configuration Field Descriptions
          3. 6.27.2.1.2 UART Boot Mode
            1. Table 6-67 UART Boot Configuration Field Descriptions
          4. 6.27.2.1.3 EMIF16 Boot Mode
            1. Table 6-68 EMIF16 Boot Configuration Field Descriptions
        2. 6.27.2.2 Serial Rapid I/O Boot Device Configuration
          1. Table 6-69 Serial Rapid I/O Configuration Field Descriptions
        3. 6.27.2.3 Ethernet (SGMII) Boot Device Configuration
          1. Table 6-70 Ethernet (SGMII) Configuration Field Descriptions
        4. 6.27.2.4 NAND Boot Device Configuration
          1. Table 6-71 NAND Configuration Field Descriptions
        5. 6.27.2.5 PCI Boot Device Configuration
          1. Table 6-72 PCI Device Configuration Field Descriptions
        6. 6.27.2.6 I2C Boot Device Configuration
          1. 6.27.2.6.1 I2C Master Mode
            1. Table 6-74 I2C Master Mode Device Configuration Field Descriptions
          2. 6.27.2.6.2 I2C Passive Mode
            1. Table 6-75 I2C Passive Mode Device Configuration Field Descriptions
        7. 6.27.2.7 SPI Boot Device Configuration
          1. Table 6-76 SPI Device Configuration Field Descriptions
        8. 6.27.2.8 HyperLink Boot Device Configuration
          1. Table 6-77 HyperLink Boot Device Configuration Field Descriptions
      3. 6.27.3 Boot Parameter Table
        1. Table 6-80 PLL Configuration Field Description
        2. 6.27.3.1   Sleep / XIP Mode Parameter Table
          1. Table 6-82 EMIF16 XIP Option Field Descriptions
        3. 6.27.3.2   SRIO Mode Boot Parameter Table
          1. Table 6-84 SRIO Boot Options Description
        4. 6.27.3.3   Ethernet Mode Boot Parameter Table
          1. Table 6-87 Ethernet Options Field Descriptions
          2. Table 6-88 SGMII Config Field Descriptions
        5. 6.27.3.4   NAND Mode Boot Parameter Table
          1. Table 6-90 NAND Boot Parameter Options Bit Field Descriptions
        6. 6.27.3.5   PCIE Mode Boot Parameter Table
          1. Table 6-92 PCIe Options Field Descriptions
        7. 6.27.3.6   I2C Mode Boot Parameter Table
          1. Table 6-94 Register Description
        8. 6.27.3.7   SPI Mode Boot Parameter Table
          1. Table 6-96 SPI Options Field Description
        9. 6.27.3.8   Hyperlink Mode Boot Parameter Table
          1. Table 6-98 Hyperlink Options Field Descriptions
        10. 6.27.3.9   UART Mode Boot Parameter Table
    28. 6.28 PLL Boot Configuration Settings
    29. 6.29 Second-Level Bootloaders
  7. 7 C66x CorePac
    1. 7.1 Memory Architecture
      1. 7.1.1 L1P Memory
      2. 7.1.2 L1D Memory
      3. 7.1.3 L2 Memory
      4. 7.1.4 MSM SRAM
      5. 7.1.5 L3 Memory
    2. 7.2 Memory Protection
    3. 7.3 Bandwidth Management
    4. 7.4 Power-Down Control
    5. 7.5 C66x CorePac Revision
      1. Table 7-2 CorePac Revision ID Register (MM_REVID) Field Descriptions
    6. 7.6 C66x CorePac Register Descriptions
  8. 8 Device Configuration
    1. 8.1 Device Configuration at Device Reset
    2. 8.2 Peripheral Selection After Device Reset
    3. 8.3 Device State Control Registers
      1. 8.3.1  Device Status Register
        1. Table 8-3 Device Status Register Field Descriptions
      2. 8.3.2  Device Configuration Register
        1. Table 8-4 Device Configuration Register Field Descriptions
      3. 8.3.3  JTAG ID (JTAGID) Register Description
        1. Table 8-5 JTAG ID Register Field Descriptions
      4. 8.3.4  Kicker Mechanism (KICK0 and KICK1) Register
      5. 8.3.5  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        1. Table 8-6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
      6. 8.3.6  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        1. Table 8-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
      7. 8.3.7  Reset Status (RESET_STAT) Register
        1. Table 8-8 Reset Status Register (RESET_STAT) Field Descriptions
      8. 8.3.8  Reset Status Clear (RESET_STAT_CLR) Register
        1. Table 8-9 Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions
      9. 8.3.9  Boot Complete (BOOTCOMPLETE) Register
        1. Table 8-10 Boot Complete Register (BOOTCOMPLETE) Field Descriptions
      10. 8.3.10 Power State Control (PWRSTATECTL) Register
        1. Table 8-11 Power State Control Register (PWRSTATECTL) Field Descriptions
      11. 8.3.11 NMI Event Generation to CorePac (NMIGRx) Register
        1. Table 8-12 NMI Generation Register (NMIGRx) Field Descriptions
      12. 8.3.12 IPC Generation (IPCGRx) Registers
        1. Table 8-13 IPC Generation Registers (IPCGRx) Field Descriptions
      13. 8.3.13 IPC Acknowledgement (IPCARx) Registers
        1. Table 8-14 IPC Acknowledgement Registers (IPCARx) Field Descriptions
      14. 8.3.14 IPC Generation Host (IPCGRH) Register
        1. Table 8-15 IPC Generation Registers (IPCGRH) Field Descriptions
      15. 8.3.15 IPC Acknowledgement Host (IPCARH) Register
        1. Table 8-16 IPC Acknowledgement Register (IPCARH) Field Descriptions
      16. 8.3.16 Timer Input Selection Register (TINPSEL)
        1. Table 8-17 Timer Input Selection Field Description (TINPSEL)
      17. 8.3.17 Timer Output Selection Register (TOUTPSEL)
        1. Table 8-18 Timer Output Selection Field Description (TOUTPSEL)
      18. 8.3.18 Reset Mux (RSTMUXx) Register
        1. Table 8-19 Reset Mux Register Field Descriptions
      19. 8.3.19 Device Speed (DEVSPEED) Register
        1. Table 8-20 Device Speed Register Field Descriptions
      20. 8.3.20 Pin Control 0 (PIN_CONTROL_0) Register
        1. Table 8-21 Pin Control 0 Register Field Descriptions
      21. 8.3.21 Pin Control 1 (PIN_CONTROL_1) Register
        1. Table 8-22 Pin Control 1 Register Field Descriptions
      22. 8.3.22 uPP Clock Source (UPP_CLOCK) Register
        1. Table 8-23 uPP Clock Source Register Field Descriptions
    4. 8.4 Pullup and Pulldown Resistors
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix
    3. 9.3 TeraNet Switch Fabric Connections
    4. 9.4 Bus Priorities
      1. 9.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register
        1. Table 9-3 Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
      2. 9.4.2 EMAC / uPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register
        1. Table 9-4 EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) Field Descriptions
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Related Links
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CZH|625
  • GZH|625
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.25 Memory Map Summary

Table 6-63 shows the memory map address ranges of the C665x device.

Table 6-63 Memory Map Summary

LOGICAL 32-BIT ADDRESS PHYSICAL 36-BIT ADDRESS BYTES DESCRIPTION
START END START END
00000000 007FFFFF 0 00000000 0 007FFFFF 8M Reserved
00800000 008FFFFF 0 00800000 0 008FFFFF 1M Local L2 SRAM
00900000 00DFFFFF 0 00900000 0 00DFFFFF 5M Reserved
00E00000 00E07FFF 0 00E00000 0 00E07FFF 32K Local L1P SRAM
00E08000 00EFFFFF 0 00E08000 0 00EFFFFF 1M-32K Reserved
00F00000 00F07FFF 0 00F00000 0 00F07FFF 32K Local L1D SRAM
00F08000 017FFFFF 0 00F08000 0 017FFFFF 9M-32K Reserved
01800000 01BFFFFF 0 01800000 0 01BFFFFF 4M C66x CorePac Registers
01C00000 01CFFFFF 0 01C00000 0 01CFFFFF 1M Reserved
01D00000 01D0007F 0 01D00000 0 01D0007F 128 Tracer_MSMC_0
01D00080 01D07FFF 0 01D00080 0 01D07FFF 32K-128 Reserved
01D08000 01D0807F 0 01D08000 0 01D0807F 128 Tracer_MSMC_1
01D08080 01D0FFFF 0 01D08080 0 01D0FFFF 32K-128 Reserved
01D10000 01D1007F 0 01D10000 0 01D1007F 128 Tracer_MSMC_2
01D10080 01D17FFF 0 01D10080 0 01D17FFF 32K-128 Reserved
01D18000 01D1807F 0 01D18000 0 01D1807F 128 Tracer_MSMC_3
01D18080 01D1FFFF 0 01D18080 0 01D1FFFF 32K-128 Reserved
01D20000 01D2007F 0 01D20000 0 01D2007F 128 Tracer_QM_DMA
01D20080 01D27FFF 0 01D20080 0 01D27FFF 32K-128 Reserved
01D28000 01D2807F 0 01D28000 0 01D2807F 128 Tracer_DDR
01D28080 01D2FFFF 0 01D28080 0 01D2FFFF 32K-128 Reserved
01D30000 01D3007F 0 01D30000 0 01D3007F 128 Tracer_SM
01D30080 01D37FFF 0 01D30080 0 01D37FFF 32K-128 Reserved
01D38000 01D3807F 0 01D38000 0 01D3807F 128 Tracer_QM_CFG
01D38080 01D3FFFF 0 01D38080 0 01D3FFFF 32K-128 Reserved
01D40000 01D4007F 0 01D40000 0 01D4007F 128 Tracer_CFG
01D40080 01D47FFF 0 01D40080 0 01D47FFF 32K-128 Reserved
01D48000 01D4807F 0 01D48000 0 01D4807F 128 Tracer_L2_0
01D48080 01D4FFFF 0 01D48080 0 01D4FFFF 32K-128 Reserved
01D50000 01D5007F 0 01D50000 0 01D5007F 128 Tracer_L2_1(C6657) or Reserved (C6655)
01D50080 01D57FFF 0 01D50080 0 01D57FFF 32K-128 Reserved
01D58000 01D5807F 0 01D58000 0 01D5807F 128 Tracer_TNet_6P_A
01D58080 021B3FFF 0 01D58080 0 021B3FFF 4464K -128 Reserved
021B4000 021B47FF 0 021B4000 0 021B47FF 2K McBSP0 Registers
021B4800 021B5FFF 0 021B4800 0 021B5FFF 6K Reserved
021B6000 021B67FF 0 021B6000 0 021B67FF 2K McBSP0 FIFO Registers
021B6800 021B7FFF 0 021B6800 0 021B7FFF 6K Reserved
021B8000 021B87FF 0 021B8000 0 021B87FF 2K McBSP1 Registers
021B8800 021B9FFF 0 021B8800 0 021B9FFF 6K Reserved
021BA000 021BA7FF 0 021BA000 0 021BA7FF 2K McBSP1 FIFO Registers
021BA800 021BFFFF 0 021BA800 0 021BFFFF 22K Reserved
021C0000 021C03FF 0 021C0000 0 021C03FF 1K TCP3d Registers
021C0400 021CFFFF 0 021C0400 0 021CFFFF 63K Reserved
021D0000 021D00FF 0 021D0000 0 021D00FF 256 VCP2_A Registers
021D0100 021D3FFF 0 021D0100 0 021D3FFF 16K - 256 Reserved
021D4000 021D40FF 0 021D4000 0 021D40FF 256 VCP2_B Registers
021D4100 021FFFFF 0 021D4100 0 021FFFFF 176K - 256 Reserved
02200000 0220007F 0 02200000 0 0220007F 128 Timer0
02200080 0220FFFF 0 02200080 0 0220FFFF 64K-128 Reserved
02210000 0221007F 0 02210000 0 0221007F 128 Reserved
02210080 0221FFFF 0 02210080 0 0221FFFF 64K-128 Reserved
02220000 0222007F 0 02220000 0 0222007F 128 Timer2
02220080 0222FFFF 0 02220080 0 0222FFFF 64K-128 Reserved
02230000 0223007F 0 02230000 0 0223007F 128 Timer3
02230080 0223FFFF 0 02230080 0 0223FFFF 64K-128 Reserved
02240000 0224007F 0 02240000 0 0224007F 128 Timer4
02240080 0224FFFF 0 02240080 0 0224FFFF 64K-128 Reserved
02250000 0225007F 0 02250000 0 0225007F 128 Timer5
02250080 0225FFFF 0 02250080 0 0225FFFF 64K-128 Reserved
02260000 0226007F 0 02260000 0 0226007F 128 Timer6
02260080 0226FFFF 0 02260080 0 0226FFFF 64K-128 Reserved
02270000 0227007F 0 02270000 0 0227007F 128 Timer7
02270080 0230FFFF 0 02270080 0 0230FFFF 640K - 128 Reserved
02310000 023101FF 0 02310000 0 023101FF 512 PLL Controller
02310200 0231FFFF 0 02310200 0 0231FFFF 64K-512 Reserved
02320000 023200FF 0 02320000 0 023200FF 256 GPIO
02320100 0232FFFF 0 02320100 0 0232FFFF 64K-256 Reserved
02330000 023303FF 0 02330000 0 023303FF 1K SmartReflex
02330400 0234FFFF 0 02330400 0 0234FFFF 127K Reserved
02350000 02350FFF 0 02350000 0 02350FFF 4K Power Sleep Controller (PSC)
02351000 0235FFFF 0 02351000 0 0235FFFF 64K-4K Reserved
02360000 023603FF 0 02360000 0 023603FF 1K Memory Protection Unit (MPU) 0
02360400 02367FFF 0 02360400 0 02367FFF 31K Reserved
02368000 023683FF 0 02368000 0 023683FF 1K Memory Protection Unit (MPU) 1
02368400 0236FFFF 0 02368400 0 0236FFFF 31K Reserved
02370000 023703FF 0 02370000 0 023703FF 1K Memory Protection Unit (MPU) 2
02370400 02377FFF 0 02370400 0 02377FFF 31K Reserved
02378000 023783FF 0 02378000 0 023783FF 1K Memory Protection Unit (MPU) 3
02378400 0237FFFF 0 02378400 0 0237FFFF 31K Reserved
02380000 023803FF 0 02380000 0 023803FF 1K Memory Protection Unit (MPU) 4
02380400 023FFFFF 0 02380400 0 023FFFFF 511K Reserved
02440000 02443FFF 0 02440000 0 02443FFF 16K DSP trace formatter 0
02444000 0244FFFF 0 02444000 0 0244FFFF 48K Reserved
02450000 02453FFF 0 02450000 0 02453FFF 16K DSP trace formatter 1 (C6657) or Reserved (C6655)
02454000 02521FFF 0 02454000 0 02521FFF 824K Reserved
02522000 02522FFF 0 02522000 0 02522FFF 4K Efuse
02523000 0252FFFF 0 02523000 0 0252FFFF 52K Reserved
02530000 0253007F 0 02530000 0 0253007F 128 I2C data and control
02530080 0253FFFF 0 02530080 0 0253FFFF 64K-128 Reserved
02540000 0254003F 0 02540000 0 0254003F 64 UART 0
02540400 0254FFFF 0 02540400 0 0254FFFF 64K-64 Reserved
02550000 0255003F 0 02550000 0 0255003F 64 UART 1
02550040 0257FFFF 0 02550040 0 0257FFFF 192K-64 Reserved
02580000 02580FFF 0 02580000 0 02580FFF 4K uPP
02581000 025FFFFF 0 02581000 0 025FFFFF 508K Reserved
02600000 02601FFF 0 02600000 0 02601FFF 8K Chip Interrupt Controller (CIC) 0
02602000 02603FFF 0 02602000 0 02603FFF 8K Reserved
02604000 02605FFF 0 02604000 0 02605FFF 8K Chip Interrupt Controller (CIC) 1
02606000 02607FFF 0 02606000 0 02607FFF 8K Reserved
02608000 02609FFF 0 02608000 0 02609FFF 8K Chip Interrupt Controller (CIC) 2
0260A000 0261FFFF 0 0260A000 0 0261FFFF 88K Reserved
02620000 026207FF 0 02620000 0 026207FF 2K Chip-Level Registers
02620800 0263FFFF 0 02620800 0 0263FFFF 126K Reserved
02640000 026407FF 0 02640000 0 026407FF 2K Semaphore
02640800 0273FFFF 0 02640800 0 0273FFFF 1022K Reserved
02740000 02747FFF 0 02740000 0 02747FFF 32K EDMA Channel Controller (EDMA3CC)
02748000 0278FFFF 0 02748000 0 0278FFFF 288K Reserved
02790000 027903FF 0 02790000 0 027903FF 1K EDMA3CC Transfer Controller EDMA3TC0
02790400 02797FFF 0 02790400 0 02797FFF 31K Reserved
02798000 027983FF 0 02798000 0 027983FF 1K EDMA3CC Transfer Controller EDMA3TC1
02798400 0279FFFF 0 02798400 0 0279FFFF 31K Reserved
027A0000 027A03FF 0 027A0000 0 027A03FF 1K EDMA3CC Transfer Controller EDMA3TC2
027A0400 027A7FFF 0 027A0400 0 027A7FFF 31K Reserved
027A8000 027A83FF 0 027A8000 0 027A83FF 1K EDMA3CC Transfer Controller EDMA3TC3
027A8400 027CFFFF 0 027A8400 0 027CFFFF 159K Reserved
027D0000 027D0FFF 0 027D0000 0 027D0FFF 4K TI embedded trace buffer (TETB) - CorePac0
027D1000 027DFFFF 0 027D1000 0 027DFFFF 60K Reserved
027E0000 027E0FFF 0 027E0000 0 027E0FFF 4K TI embedded trace buffer (TETB) - CorePac1 (C6657) or Reserved (C6655)
027E1000 0284FFFF 0 027E1000 0 0284FFFF 444K Reserved
02850000 02857FFF 0 02850000 0 02857FFF 32K TI embedded trace buffer (TETB) — system
02858000 028FFFFF 0 02858000 0 028FFFFF 672K Reserved
02900000 02920FFF 0 02900000 0 02920FFF 132K Serial RapidIO (SRIO) configuration
02921000 029FFFFF 0 02921000 0 029FFFFF 1M-132K Reserved
02A00000 02AFFFFF 0 02A00000 0 02AFFFFF 1M Queue manager subsystem configuration
02B00000 02C07FFF 0 02B00000 0 02C07FFF 1056K Reserved
02C08000 02C8BFFF 0 02C08000 0 02C8BFFF 16K EMAC subsystem configuration
02C0C000 07FFFFFF 0 02C0C000 0 07FFFFFF 84M - 48K Reserved
08000000 0800FFFF 0 08000000 0 0800FFFF 64K Extended memory controller (XMC) configuration
08010000 0BBFFFFF 0 08010000 0 0BBFFFFF 60M-64K Reserved
0BC00000 0BCFFFFF 0 0BC00000 0 0BCFFFFF 1M Multicore shared memory controller (MSMC) config
0BD00000 0BFFFFFF 0 0BD00000 0 0BFFFFFF 3M Reserved
0C000000 0C0FFFFF 0 0C000000 0 0C0FFFFF 1M Multicore shared memory (MSM)
0C200000 107FFFFF 0 0C100000 0 107FFFFF 71 M Reserved
10800000 108FFFFF 0 10800000 0 108FFFFF 1M CorePac0 L2 SRAM
10900000 10DFFFFF 0 10900000 0 10DFFFFF 5M Reserved
10E00000 10E07FFF 0 10E00000 0 10E07FFF 32K CorePac0 L1P SRAM
10E08000 10EFFFFF 0 10E08000 0 10EFFFFF 1M-32K Reserved
10F00000 10F07FFF 0 10F00000 0 10F07FFF 32K CorePac0 L1D SRAM
10F08000 117FFFFF 0 10F08000 0 117FFFFF 9M-32K Reserved
11800000 118FFFFF 0 11800000 0 118FFFFF 1M CorePac1 L2 SRAM (C6657) or Reserved (C6655)
11900000 11DFFFFF 0 11900000 0 11DFFFFF 5M Reserved
11E00000 11E07FFF 0 11E00000 0 11E07FFF 32K CorePac1 L1P SRAM (C6657) or Reserved (C6655)
11E08000 11EFFFFF 0 11E08000 0 11EFFFFF 1M-32K Reserved
11F00000 11F07FFF 0 11F00000 0 11F07FFF 32K CorePac1 L1D SRAM (C6657) or Reserved (C6655)
11F08000 1FFFFFFF 0 11F08000 0 1FFFFFFF 225M-32K Reserved
20000000 200FFFFF 0 20000000 0 200FFFFF 1M System trace manager (STM) configuration
20100000 207FFFFF 0 20100000 0 207FFFFF 7M Reserved
20800000 208FFFFF 0 20080000 0 208FFFFF 1M TCP3d Data
20900000 20AFFFFF 0 20900000 0 20AFFFFF 2M Reserved
20B00000 20B1FFFF 0 20B00000 0 20B1FFFF 128K Boot ROM
20B20000 20BEFFFF 0 20B20000 0 20BEFFFF 832K Reserved
20BF0000 20BF01FF 0 20BF0000 0 20BF01FF 512 SPI
20BF0400 20BFFFFF 0 20BF0200 0 20BFFFFF 64K -512 Reserved
20C00000 20C000FF 0 20C00000 0 20C000FF 256 EMIF16 configuration
20C00100 20FFFFFF 0 20C00100 0 20FFFFFF 4M - 256 Reserved
21000000 210001FF 1 00000000 1 000001FF 512 DDR3 EMIF configuration
21000200 213FFFFF 0 21000200 0 213FFFFF 4M-512 Reserved
21400000 214000FF 0 21400000 0 214000FF 256 HyperLink config
21400100 217FFFFF 0 21400100 0 217FFFFF 4M-256 Reserved
21800000 21807FFF 0 21800000 0 21807FFF 32K PCIe config
21808000 33FFFFFF 0 21808000 0 33FFFFFF 8M-32K Reserved
22000000 22000FFF 0 22000000 0 22000FFF 4K McBSP0 FIFO Data
22000100 223FFFFF 0 22000100 0 223FFFFF 4M-4K Reserved
22400000 22400FFF 0 22400000 0 22400FFF 4K McBSP1 FIFO Data
22400100 229FFFFF 0 22400100 0 229FFFFF 6M-4K Reserved
22A00000 22A0FFFF 0 22A00000 0 22A0FFFF 64K VCP2_A
22A01000 22AFFFFF 0 22A01000 0 22AFFFFF 1M-64K Reserved
22B00000 22B0FFFF 0 22B00000 0 22B0FFFF 64K VCP2_B
22B01000 33FFFFFF 0 22B01000 0 33FFFFFF 277M-64K Reserved
34000000 341FFFFF 0 34000000 0 341FFFFF 2M Queue manager subsystem data
34200000 3FFFFFFF 0 34200000 0 3FFFFFFF 190M Reserved
40000000 4FFFFFFF 0 40000000 0 4FFFFFFF 256M HyperLink data
50000000 5FFFFFFF 0 50000000 0 5FFFFFFF 256M Reserved
60000000 6FFFFFFF 0 60000000 0 6FFFFFFF 256M PCIe data
70000000 73FFFFFF 0 70000000 0 73FFFFFF 64M EMIF16 CE0 data space, supports NAND, NOR, or SRAM memory(1)
74000000 77FFFFFF 0 74000000 0 77FFFFFF 64M EMIF16 CE1 data space, supports NAND, NOR, or SRAM memory(1)
78000000 7BFFFFFF 0 78000000 0 7BFFFFFF 64M EMIF16 CE2 data space, supports NAND, NOR, or SRAM memory(1)
7C000000 7FFFFFFF 0 7C000000 0 7FFFFFFF 64M EMIF16 CE3 data space, supports NAND, NOR or SRAM memory(1)
80000000 FFFFFFFF 8 00000000 8 7FFFFFFF 2G DDR3 EMIF data(2)
(1) 32MB per chip select for 16-bit NOR and SRAM. 16MB per chip select for 8-bit NOR and SRAM. The 32MB and 16MB size restrictions do not apply to NAND.
(2) The memory map only shows the default MPAX configuration of DDR3 memory space. For the extended DDR3 memory space access (up to 4GB), see the MPAX configuration details in C66x CorePac User's Guide and Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide in Section 10.3.