SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Byte Offset | Name | Decription |
---|---|---|
12 | Options | See Figure 6-44 |
14 | I2cClkFreqKhz | The I2C clock frequency to use when using I2C tables |
16 | I2cTargetAddr | The I2C bus address of the EEPROM |
18 | I2cLocalAddr | The I2C bus address of the Appleton device |
20 | I2cDataAddr | The address on the EEPROM of the NAND configuration table |
22 | I2cWtoRDelay | Delay between addres writes and data reads, in I2C clock periods |
24 | csNum | The NAND chip-select region (0-3) |
26 | firstBlock | The first block of the boot image |
15 | 1 | 0 |
Reserved | I2C |
Name | Value | Description |
---|---|---|
I2C | 0 | NAND configuration is NOT read from I2C |
1 | NAND configuration is read from the I2C |