SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Extra device configuration is provided in the PCI bits in the DEVSTAT register. PCI boot is shown in Figure 6-34 and described in Table 6-72 and Table 6-73.
9 | 8 | 7 | 6 | 5 | 4 | 3 |
Ref Clock | BAR Config | Reserved |
Bit | Field | Description |
---|---|---|
9 | Ref Clock | PCIe reference clock configuration
|
8-5 | BAR Config | PCIe BAR registers configuration
This value can range from 0 to 0xf. See Table 6-73. |
4-3 | Reserved | Reserved |
BAR CFG | BAR0 | 32-BIT ADDRESS TRANSLATION | 64-BIT ADDRESS TRANSLATION | |||||
---|---|---|---|---|---|---|---|---|
BAR1 | BAR2 | BAR3 | BAR4 | BAR5 | BAR2/3 | BAR4/5 | ||
0b0000 | PCIe MMRs | 32 | 32 | 32 | 32 | Clone of BAR4 | ||
0b0001 | 16 | 16 | 32 | 64 | ||||
0b0010 | 16 | 32 | 32 | 64 | ||||
0b0011 | 32 | 32 | 32 | 64 | ||||
0b0100 | 16 | 16 | 64 | 64 | ||||
0b0101 | 16 | 32 | 64 | 64 | ||||
0b0110 | 32 | 32 | 64 | 64 | ||||
0b0111 | 32 | 32 | 64 | 128 | ||||
0b1000 | 64 | 64 | 128 | 256 | ||||
0b1001 | 4 | 128 | 128 | 128 | ||||
0b1010 | 4 | 128 | 128 | 256 | ||||
0b1011 | 4 | 128 | 256 | 256 | ||||
0b1100 | 256 | 256 | ||||||
0b1101 | 512 | 512 | ||||||
0b1110 | 1024 | 1024 | ||||||
0b1111 | 2048 | 2048 |