SPRS565D April 2009 – June 2014 TMS320C6743
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock alignment, and test points.
PLLC0 generates several clocks from the PLL0 output clock for use by the various modules. These are summarized in Table 6-5. The clock ratios between SYSCLK1, SYSCLK2, SYSCLK4 and SYSCLK6 must always be maintained as shown in the table.
OUTPUT CLOCK | USED BY | DEFAULT RATIO (RELATIVE TO SYSCLK1) | NOTES |
---|---|---|---|
SYSCLK1 | DSP | /1 | No Required Ratio |
SYSCLK2 | EDMA, DSP ports, EMIFB (ports to switch fabric), ECAP 0/1/2, EPWM 0/1/2, EQEP 0/1, McASP/FIFO 0/1, UART 2, HRPWM 0/1/2, SPI0 | /2 | SYSCLK1 / 2 |
SYSCLK3 | EMIFA | /3 | No Required Ratio |
SYSCLK4 | SYSCFG, Interrupt Controller, PLLC0, PSC 0, EMAC/MDIO, GPIO, I2C 1, PSC 1 | /4 | SYSCLK1 / 4 |
SYSCLK5 | EMIFB | /3 | No Required Ratio |
SYSCLK7 | RMII clock to EMAC | /6 | No Required Ratio ;
Should be set to 50 MHz |
AUXCLK | McASP AuxClk, Timer64P0,Timer64P1, I2C0, | N/A | No Required Ratio |
DIV4p5 | 133MHz clock source for EMIFB | PLL output/4.5 | No Required Ratio |