SPRS565D April 2009 – June 2014 TMS320C6743
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
NO. | MIN | MAX | UNIT | |||
---|---|---|---|---|---|---|
1 | tc(SPC)M | Cycle Time, SPI0_CLK, All Master Modes | greater of 3P or 20 | 256P | ns | |
2 | tw(SPCH)M | Pulse Width High, SPI0_CLK, All Master Modes | 0.5tc(SPC)M - 1 | ns | ||
3 | tw(SPCL)M | Pulse Width Low, SPI0_CLK, All Master Modes | 0.5tc(SPC)M - 1 | ns | ||
4 | td(SIMO_SPC)M | Delay, initial data bit valid on SPI0_SIMO after initial edge on SPI0_CLK(2) | Polarity = 0, Phase = 0,
to SPI0_CLK rising |
5 | ns | |
Polarity = 0, Phase = 1,
to SPI0_CLK rising |
-0.5tc(SPC)M + 5 | |||||
Polarity = 1, Phase = 0,
to SPI0_CLK falling |
5 | |||||
Polarity = 1, Phase = 1,
to SPI0_CLK falling |
-0.5tc(SPC)M + 5 | |||||
5 | td(SPC_SIMO)M | Delay, subsequent bits valid on SPI0_SIMO after transmit edge of SPI0_CLK | Polarity = 0, Phase = 0,
from SPI0_CLK rising |
5 | ns | |
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
5 | |||||
Polarity = 1, Phase = 0,
from SPI0_CLK falling |
5 | |||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
5 | |||||
6 | toh(SPC_SIMO)M | Output hold time, SPI0_SIMO valid after
receive edge of SPI0_CLK |
Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5tc(SPC)M -3 | ns | |
Polarity = 0, Phase = 1,
from SPI0_CLK rising |
0.5tc(SPC)M -3 | |||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5tc(SPC)M -3 | |||||
Polarity = 1, Phase = 1,
from SPI0_CLK falling |
0.5tc(SPC)M -3 | |||||
7 | tsu(SOMI_SPC)M | Input Setup Time, SPI0_SOMI valid before
receive edge of SPI0_CLK |
Polarity = 0, Phase = 0,
to SPI0_CLK falling |
0 | ns | |
Polarity = 0, Phase = 1,
to SPI0_CLK rising |
0 | |||||
Polarity = 1, Phase = 0,
to SPI0_CLK rising |
0 | |||||
Polarity = 1, Phase = 1,
to SPI0_CLK falling |
0 | |||||
8 | tih(SPC_SOMI)M | Input Hold Time, SPI0_SOMI valid after
receive edge of SPI0_CLK |
Polarity = 0, Phase = 0,
from SPI0_CLK falling |
5 | ns | |
Polarity = 0, Phase = 1,
from SPI0_CLK rising |
5 | |||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
5 | |||||
Polarity = 1, Phase = 1,
from SPI0_CLK falling |
5 |