Table 6-10 Timing Requirements for GPIO Inputs(1) (see Figure 6-10)
NO. |
|
MIN |
MAX |
UNIT |
1 |
tw(GPIH) |
Pulse duration, GPIx high |
2C(1)(2) |
|
ns |
2 |
tw(GPIL) |
Pulse duration, GPIx low |
2C(1)(2) |
|
|
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device enough time to access the GPIO register through the internal bus.