SPRS867A February   2013  – August 2016 TMS320DM369

PRODUCTION DATA.  

  1. 1TMS320DM369 Digital Media System-on-Chip (DMSoC)
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Comparison
    2. 3.2 Device Characteristics
    3. 3.3 Device Compatibility
    4. 3.4 ARM Subsystem Overview
      1. 3.4.1  Components of the ARM Subsystem
      2. 3.4.2  ARM926EJ-S RISC CPU
      3. 3.4.3  CP15
      4. 3.4.4  MMU
      5. 3.4.5  Caches and Write Buffer
      6. 3.4.6  Tightly Coupled Memory (TCM)
      7. 3.4.7  Advanced High-performance Bus (AHB)
      8. 3.4.8  Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      9. 3.4.9  ARM Memory Mapping
        1. 3.4.9.1 ARM Internal Memories
        2. 3.4.9.2 External Memories
      10. 3.4.10 Peripherals
      11. 3.4.11 ARM Interrupt Controller (AINTC)
    5. 3.5 System Control Module
    6. 3.6 Power Management
    7. 3.7 Memory Map Summary
    8. 3.8 Pin Assignments
      1. 3.8.1 Pin Map (Bottom View)
    9. 3.9 Terminal Functions
  4. 4Device Configurations
    1. 4.1 System Module Registers
    2. 4.2 Boot Modes
      1. 4.2.1 Boot Modes Overview
    3. 4.3 Device Clocking
      1. 4.3.1 Overview
      2. 4.3.2 PLL Controller Module
      3. 4.3.3 PLLC1
      4. 4.3.4 PLLC2
      5. 4.3.5 Processing, Video, EDMA and DDR EMIF Subsystems Maximum Operating Frequencies
      6. 4.3.6 PLL Controller Clocking Configurations Examples
      7. 4.3.7 Peripheral Clocking Considerations
    4. 4.4 Power and Sleep Controller (PSC)
    5. 4.5 Pin Multiplexing
    6. 4.6 Device Reset
    7. 4.7 Default Device Configurations
      1. 4.7.1 Device Configuration Pins
      2. 4.7.2 PLL Configuration
      3. 4.7.3 Power Domain and Module State Configuration
      4. 4.7.4 ARM Boot Mode Configuration
      5. 4.7.5 AEMIF Configuration
        1. 4.7.5.1 AEMIF Pin Configuration
        2. 4.7.5.2 AEMIF Timing Configuration
      6. 4.7.6 Oscillator Frequency Configuration
    8. 4.8 Debugging Considerations
      1. 4.8.1 Pullup/Pulldown Resistors
  5. 5System Interconnect
  6. 6Device Operating Conditions
    1. 6.1 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Parameter Information Device-Specific Information
      1. 7.1.1 Signal Transition Levels
      2. 7.1.2 Timing Parameters and Board Routing Analysis
    2. 7.2  Recommended Clock and Control Signal Transition Behavior
    3. 7.3  Power Supplies
    4. 7.4  Power-Supply Sequencing
      1. 7.4.1 Simple Power-On and Power-Off Method
      2. 7.4.2 Restricted Power-On and Power-Off Method
      3. 7.4.3 Power-Supply Design Considerations
      4. 7.4.4 Power-Supply Decoupling
    5. 7.5  Reset
      1. 7.5.1 Reset Electrical Data/Timing
    6. 7.6  Oscillators and Clocks
      1. 7.6.1 MXI1 Oscillator
      2. 7.6.2 Clock PLL Electrical Data/Timing (Input and Output Clocks)
      3. 7.6.3 PRTCSS Oscillator
      4. 7.6.4 PRTCSS Electrical Data/Timing
    7. 7.7  Power Management and Real Time Clock Subsystem (PRTCSS)
      1. 7.7.1 PRTCSS Peripheral Register Description
    8. 7.8  General-Purpose Input/Output (GPIO)
      1. 7.8.1 GPIO Peripheral Register Description
      2. 7.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 7.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    9. 7.9  EDMA Controller
      1. 7.9.1 EDMA Channel Synchronization Events
      2. 7.9.2 EDMA Peripheral Register Description
    10. 7.10 External Memory Interface (EMIF)
      1. 7.10.1 Asynchronous EMIF (AEMIF)
        1. 7.10.1.1 NAND (NAND, SmartMedia, xD)
        2. 7.10.1.2 OneNAND
        3. 7.10.1.3 EMIF Peripheral Register Descriptions
        4. 7.10.1.4 AEMIF Electrical Data/Timing
      2. 7.10.2 DDR2/mDDR Memory Controller
      3. 7.10.3 DDR2/mDDR Memory Controller Electrical Data/Timing
        1. 7.10.3.1 DDR2/mDDR Routing Specifications
          1. 7.10.3.1.1  DDR2/mDDR Interface
          2. 7.10.3.1.2  DDR2/mDDR Interface Schematic
          3. 7.10.3.1.3  Compatible JEDEC DDR2/mDDR Devices
          4. 7.10.3.1.4  PCB Stack Up
          5. 7.10.3.1.5  Placement
          6. 7.10.3.1.6  DDR2/mDDR Keep Out Region
          7. 7.10.3.1.7  Bulk Bypass Capacitors
          8. 7.10.3.1.8  High-Speed Bypass Capacitors
          9. 7.10.3.1.9  Net Classes
          10. 7.10.3.1.10 DDR2/mDDR Signal Termination
          11. 7.10.3.1.11 VREF Routing
          12. 7.10.3.1.12 DDR2/mDDR CK and ADDR_CTRL Routing
    11. 7.11 MMC/SD
      1. 7.11.1 MMC/SD Peripheral Register Description
      2. 7.11.2 MMC/SD Electrical Data/Timing
    12. 7.12 Video Processing Subsystem (VPSS) Overview
      1. 7.12.1 Video Processing Front-End (VPFE)
        1. 7.12.1.1 Image Sensor Interface (ISIF)
        2. 7.12.1.2 The Image Pipe Interface (IPIPEIF)
        3. 7.12.1.3 Image Pipe - Hardware Image Signal Processor (IPIPE)
        4. 7.12.1.4 Hardware 3A (H3A)
        5. 7.12.1.5 Face Detection Module
        6. 7.12.1.6 VPFE Electrical Data/Timing
      2. 7.12.2 Video Processing Back-End (VPBE)
        1. 7.12.2.1 On-Screen Display (OSD)
        2. 7.12.2.2 Video Encoder / Digital LCD Controller (VENC/DLCD)
        3. 7.12.2.3 VPBE Electrical Data/Timing
        4. 7.12.2.4 High-Definition (HD) DACs and Video Buffer Electrical Data/Timing
          1. 7.12.2.4.1 HD DACs-Only Option
          2. 7.12.2.4.2 DAC With Video Buffer Option
    13. 7.13 USB2.0
      1. 7.13.1 USB Peripheral Register Description
      2. 7.13.2 USB2.0 Electrical Data/Timing
    14. 7.14 Universal Asynchronous Receiver/Transmitter (UART)
      1. 7.14.1 UART Peripheral Register Description
      2. 7.14.2 UART Electrical Data/Timing
    15. 7.15 Serial Port Interface (SPI)
      1. 7.15.1 SPI Peripheral Register Description
      2. 7.15.2 SPI Electrical Data/Timing
        1. 7.15.2.1 Master Mode — General
        2. 7.15.2.2 Slave Mode — General
        3. 7.15.2.3 Master Mode — Additional
        4. 7.15.2.4 Slave Mode — Additional
    16. 7.16 Inter-Integrated Circuit (I2C)
      1. 7.16.1 I2C Peripheral Register Description
      2. 7.16.2 I2C Electrical Data/Timing
        1. 7.16.2.1 Inter-Integrated Circuits (I2C) Timing
    17. 7.17 Multichannel Buffered Serial Port (McBSP)
      1. 7.17.1 McBSP Peripheral Register Description
      2. 7.17.2 McBSP Electrical Data/Timing
        1. 7.17.2.1 multichannel Buffered Serial Port (McBSP) Timing
    18. 7.18 Timer
      1. 7.18.1 Timer Peripheral Register Description
      2. 7.18.2 Timer Electrical Data/Timing
    19. 7.19 Pulse Width Modulator (PWM)
      1. 7.19.1 PWM Peripheral Register Description
      2. 7.19.2 PWM0/1/2/3 Electrical/Timing Data
    20. 7.20 Real Time Out (RTO)
      1. 7.20.1 Real Time Out (RTO) Peripheral Register Description
      2. 7.20.2 RTO Electrical/Timing Data
    21. 7.21 Ethernet Media Access Controller (EMAC)
      1. 7.21.1 EMAC Peripheral Register Description
      2. 7.21.2 Ethernet Media Access Controller (EMAC) Electrical Data/Timing
    22. 7.22 Management Data Input/Output (MDIO)
      1. 7.22.1 MDIO Peripheral Register Description
      2. 7.22.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    23. 7.23 Host-Port Interface (HPI) Peripheral
      1. 7.23.1 HPI Device-Specific Information
      2. 7.23.2 HPI Bus Master
      3. 7.23.3 HPI Peripheral Register Description
      4. 7.23.4 HPI Electrical Data/Timing
    24. 7.24 Key Scan
      1. 7.24.1 Key Scan Peripheral Register Description
        1. 7.24.1.1 Key Scan Registers
      2. 7.24.2 Key Scan Electrical Data/Timing
    25. 7.25 Analog-to-Digital Converter (ADC)
      1. 7.25.1 Analog-to-Digital Converter (ADC) Peripheral Register Description
        1. 7.25.1.1 Analog-to-Digital Converter (ADC) Interface Registers
    26. 7.26 Voice Codec
      1. 7.26.1 Voice Codec Register Description
        1. 7.26.1.1 Voice Codec Registers
    27. 7.27 IEEE 1149.1 JTAG
      1. 7.27.1 JTAG Register Description
      2. 7.27.2 JTAG Test-Port Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Development Tools
    2. 8.2 Device Nomenclature
    3. 8.3 Documentation Support
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information
    2. 9.2 Thermal Data for ZCE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCE|338
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 TMS320DM369 Digital Media System-on-Chip (DMSoC)

1.1 Features

  • High-Performance Digital Media System-on-Chip (DMSoC)
    • 432-MHz ARM®ARM926EJ-S™ Clock Rate
    • 4:2:2 (8- and 16-Bit) Interface
    • Capable of 1080 p 30 fps H.264 Video Processing
    • Pin Compatible With DM365, DM368, DMVA1, and DMVA2 Processors
    • Fully Software-Compatible With ARM9™
    • Extended Temperature Available for 432-MHz Device
    • Supports TI Third-Generation Noise Filter
    • Supports SMART Codec Feature for Very Low Bitrate
  • ARM® ARM926EJ-S™ Core
    • Support for 32-Bit and 16-Bit
      (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single-Cycle MAC
    • ARM® Jazelle® Technology
    • Embedded ICE-RT Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 8KB of Data Cache
    • 32KB of RAM
    • 16KB of ROM
    • Little Endian
  • Three Video Image Coprocessors
    (Noise Filtering, HDVICP, MJCP) Engines
    • Supports a Range of Encode and Decode Operations
    • H.264, MPEG-4, MPEG-2, MJPEG, JPEG, WMV9 (VC-1)
    • Noise Filtering Engine
  • Video Processing Subsystem
    • Front End Provides:
      • Hardware Face Detect Engine
      • Hardware IPIPE for Real-Time Image Processing
        • Resize Engine
          • Resize Images From 1/16x to 8x
          • Separate Horizontal and Vertical Control
          • Two Simultaneous Output Paths
      • IPIPE Interface (IPIPEIF)
      • Image Sensor Interface (ISIF) and CMOS Imager Interface
      • 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
      • Glueless Interface to Common Video Decoders
      • BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8- and 16-Bit) Interface
      • Histogram Module
      • Lens Distortion Correction (LDC) Module
      • Hardware 3A Statistics Collection Module (H3A)
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL Video Encoder Output
      • 8- and 16-Bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 Digital-to-Analog Converters (DACs) for HD Analog Video Output
      • LCD Controller
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8- and 16-Bit) Interface
  • Analog-to-Digital Converter (ADC)
  • Power Management and Real-Time Clock Subsystem (PRTCSS)
    • Real-Time Clock (RTC)
  • 16-Bit Host Port Interface (HPI)
  • 10/100 Mbps Ethernet Media Access Controller (EMAC) - Digital Media
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • Key Scan
  • Voice Codec
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-Bit-Wide EMIF With 256MB of Address Space (1.8-V I/O)
    • Asynchronous 16- and 8-Bit-Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8- and 16-Bit-Wide Data)
        • 16MB of NOR Flash, SRAM
        • OneNAND (16-Bit-Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia/xD
  • Enhanced Direct Memory Access (EDMA) Controller (64 Independent Channels)
  • USB Port With Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 High-Speed Device
    • USB 2.0 High-Speed Host (Mini-Host, Supporting One External Device)
    • USB On The Go (HS-USB OTG)
  • Four 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watchdog Timer
  • Two UARTs (One Fast UART With RTS and CTS Flow Control)
  • Five Serial Port Interfaces (SPIs) Each With Two Chip Selects
  • One Master or Slave Inter-Integrated Circuit (I2C) Bus™
  • One Multichannel Buffered Serial Port (McBSP)
    • I2S
    • AC97 Audio Codec Interface
    • S/PDIF Through Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
    • Direct Interface to T1 (E1) Framers
    • Time Division Multiplexed (TDM) Mode
    • 128-Channel Mode
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real-Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Boot Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
    • AEMIF (NOR and OneNAND)
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (Typically 19.2, 24, 27, or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE 1149.1 (JTAG) Boundary-Scan-Compatible
    • ETB (Embedded Trace Buffer) With 4KB of Trace Buffer Memory
    • Device Revision ID Readable by ARM
  • 338-Pin Ball Grid Array (BGA) Package
    (ZCE Suffix), 0.65-mm Ball Pitch
  • 65-nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.35-V Internal

1.2 Applications

  • IP Cameras
  • Machine Vision Cameras
  • Ultra-Low Power Portable Cameras
  • Intrusion Panels With Video
  • Access Control Panels With Video
  • Fire Panels With Video
  • Video Door Bells
  • Video IP Phones
  • USB Web Cameras
  • Media Players and Adapters
  • Network Projectors
  • Home Audio and Video Equipment
  • Portable Medical Imaging and Patient Monitoring
  • Camcorders
  • Digital Photo Frames

1.3 Description

Developers can now deliver crystal-clear multiformat video at up to 1080 p H.264 at 30 fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM369 DaVinci™ video processors from TI.

The DM369 device is uniquely capable of running TI’s third-generation noise filtering technology while achieving low-light HD H.264 720p30 video compression and is pin-to-pin compatible with the DM365 processors, using the same ARM ARM926EJ-S core running at 432 MHz. This ARM9-based DM369 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG, and WMV9 (VC-1) codecs providing customers with the flexibility to select the correct video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This lets developers obtain optimal performance from the ARM for their applications, including their multichannel, multistream, and multiformat needs.

Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players, and more can take advantage of the low power consumption and can ensure interoperability and product scalability by taking advantage of the full suite of codecs supported on the DM369 device.

Along with multiformat HD video, the DM369 processor also features a suite of peripherals that reduces system cost and complexity, thus enabling a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM369 device also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to-digital converter (ADC), and many more features that reduce overall system costs and save real estate on circuit boards, thus allowing for a slimmer, sleeker design.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
TMS320DM369ZCE NFBGA (338) 13.00 mm × 13.00 mm
(1) For more information on these devices, see Section 9, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the TMS320DM369 device.

TMS320DM369 fbd_dm369_2.gif Figure 1-1 Functional Block Diagram