Table 3-1 Device Comparison

Table 3-2 Characteristics of the Processor

3.2.1 ARM Cortex-A8 RISC Processor

The ARM Cortex-A8 subsystem integrates the ARM Cortex-A8 processor. The ARM Cortex-A8 processor is a member of ARM Cortex family of general-purpose processors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM Cortex-A8 processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM Cortex-A8 processor has a Harvard architecture and provides a complete high-performance subsystem, including:

• ARM Cortex-A8 integer core
• Superscalar ARMv7 instruction set
• Thumb-2 instruction set
• Jazelle RCT acceleration
• CP14 debug coprocessor
• CP15 system control coprocessor
• NEON 64-bit and 128-bit hybrid SIMD engine for multimedia
• Enhanced memory management unit (MMU)
• Separate level-1 instruction and data caches
• Integrated level-2 cache
• 128-bit interconnect to system memories and peripherals
• Embedded trace module (ETM).

3.2.2 Embedded Trace Module (ETM)

To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an embedded trace module (ETM). The ETM consists of two parts:

• The Trace port provides real-time trace capability for the ARM Cortex-A8.
• Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers.

The ARM Cortex-A8 trace port is connected to the system-level embedded trace buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are required to read and interpret the captured trace data.

For more details on the ETB, see Section 9.4.2.

3.2.3 ARM Cortex-A8 Interrupt Controller (AINTC)

The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor. For more details on the AINTC, see Section 8.4.

3.2.4 System Interconnect

The ARM Cortex-A8 processor in connected through the arbiter to both an L3 interconnect port and a DMM port. The DMM port is 128-bits wide and provides the ARM Cortex-A8 direct access to the DDR memories, while the L3 interconnect port is 64-bits wide and provides access to the remaining device modules.

3.3.1 C674x DSP CPU Description

The C674x central processing unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 3-3. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the C67x+ core.

Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add and subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add and subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add and subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C674x core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit and 16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.
• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.
• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).
• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.
• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C674x CPU and its enhancements over the C64x architecture, see the following documents:

• TMS320C674x DSP CPU and Instruction Set User's Guide (literature number SPRUFE8)
• TMS320C674x DSP Megamodule Reference Guide (literature number SPRUFK5)

Figure 3-3 TMS320C674x CPU (DSP Core) Data Paths

3.3.2 System Memory Management Unit (System MMU)

All C674x DSP accesses through the MDMA port are directed through the system memory management unit (System MMU) module where they are remapped to physical system addresses. This protects the ARM Cortex-A8 memory regions from accidental corruption by C674x code and allows for direct allocation of buffers in user space without the need for translation between ARM and DSP applications.

In addition, accesses by the EDMA TC0 may optionally be routed through the System MMU. This allows EDMA Channel 0 to be used by the DSP to perform transfers using only the known virtual addresses of the associated buffers. The MMU_CFG register in the Control Module is used to enable and disable use of the DSP EDMA MMU by the EDMA TC.

For details on the System MMU features and registers, see the System MMU chapter of the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (literature number SPRUGX8).

3.6.1 Mailbox Module

The device Mailbox module facilitates communication between the ARM Cortex-A8, C674x DSP, and the Media Controller. It consists of twelve mailboxes, each supporting communication between two of the above processors. The sender sends information to the receiver by writing a message to the mailbox registers. Interrupt signaling is used to notify the receiver that a message has been queued or to notify the sender about an overflow situation.

The Mailbox module supports the following features (see Figure 3-4):

• 12 mailboxes
• Four-message FIFO depth for each message queue
• 32-bit message width
• Message reception and queue-not-full notification using interrupts
• Four interrupts (one to ARM Cortex-A8, one to C674x, two to Media Controller).

Figure 3-4 Mailbox Module Block Diagram

3.6.2 Spinlock Module

The Spinlock module provides hardware assistance for synchronizing the processes running on multiple processors in the device:

• ARM Cortex-A8 processor
• C674x DSP
• Media Controller processors.

The Spinlock module implements 64 spinlocks (or hardware semaphores) that provide an efficient way to perform a lock operation of a device resource using a single read-access, avoiding the need for a read-modify-write bus transfer of which the programmable cores are not capable.

Table 3-7 PRCM Register Address Summary

Table 3-8 PRM_DEVICE Register Summary

Table 3-9 CM_DEVICE Register Summary

Table 3-10 OCP_SOCKET_PRM Register Summary

Table 3-11 CM_DPLL Register Summary

Table 3-12 CM_ACTIVE Register Summary

Table 3-13 CM_DEFAULT Register Summary

Table 3-14 CM_IVAHD0 Register Summary

Table 3-15 CM_IVAHD1 Register Summary

Table 3-16 CM_IVAHD2 Register Summary

Table 3-17 CM_SGX Register Summary

Table 3-18 PRM_ACTIVE Register Summary

Table 3-19 PRM_DEFAULT Register Summary

Table 3-20 PRM_IVAHD0 Register Summary

Table 3-21 PRM_IVAHD1 Register Summary

Table 3-22 PRM_IVAHD2 Register Summary

Table 3-23 PRM_SGX Register Summary

Table 3-24 CM_ALWON Register Summary

Table 3-25 PRM_ALWON Register Summary

3.9.1 L3 Memory Map

The L3 high-performance interconnect is based on a Network-on-Chip (NoC) interconnect infrastructure. The NoC uses an internal packet-based protocol for forward (read command, write command with data payload) and backward (read response with data payload, write response) transactions. All exposed interfaces of this NoC interconnect, both for targets and initiators, comply with the OCPIP2.2 reference standard.

Table 3-26 shows the general device level-3 (L3) memory map. The table represents the physical addresses used by the L3 infrastructure. Some processors within the device (such as Cortex™-A8 ARM, C674x DSP) may re-map these targets to different virtual addresses through an internal or external MMU. Processors without MMUs and other bus masters use these physical addresses to access L3 regions. Note that not all masters have access to all L3 regions, but only those with defined connectivity, as shown in Table 7-1. For a list of the specific peripherals attached to each of the Level-4 (L4) peripheral ports see Section 7.2. The L3 interconnect returns an address-hole error if any initiator attempts to access a target to which it has no connection.

1. The first section of GPMC memory (0x0 - 0x00FF_FFFF) is reserved for BOOTROM. Accessible memory starts at location 0x0100_0000.
2. For more information about McASP registers accessed through the DAT port, see notes-list-normal.
3. These accesses occur through the DDR DMM Tiler Ports. The DMM will split address ranges internally to address DDR EMIF and DDR DMM control registers.
4. DDR EMIF0 and DDR EMIF1 addresses may be contiguous or bank interleaved depending on configuration of the DDR DMM; for more details, see the DDR DMM documentation.

3.9.2 L4 Memory Map

3.9.3 TILER Extended Addressing Map

The Tiling and Isometric Lightweight Engines for Rotation (TILER) ports are mainly used for optimized 2-D block accesses. The TILER also supports rotation of the image buffer at 0º, 90º, 180º, and 270º, with vertical and horizontal mirroring.

The TILER includes an additional 4-GB addressing range to access the frame buffer in these rotated and mirrored views. This range requires a thirty-third bit of address and is only accessible to peripherals that require access to the multiple views. On the device, this is limited to the HD Video Processing Subsystem (HDVPSS). (Other peripherals, based on ConnID, may access any one single view through the 512-MB TILER window region located in the base 4-GB range.)

The HDVPSS may use the virtual address space of 4GB (0x1:0000:0000 – 0x1:FFFF:FFFF) since various VPDMA clients of the HDVPSS may need to simultaneously access multiple 2-D images with different orientations of the image buffers.

The top 4-GB address space is divided into eight sections of 512MB each. These eight sections correspond to the eight different orientations as shown in Table 3-29.

3.9.4 Cortex™-A8 Memory Map

The Cortex™-A8 includes an memory management unit (MMU) to translate virtual addresses to physical addresses which are then decoded within the Host ARM Subsystem. The subsystem includes its own ROM and RAM, as well as configuration registers for its interrupt controller. These addresses are hard-coded within the subsystem. In addition, the upper 2GB of address space is routed to a special port (Master 0) intended for low-latency access to DDR memory. All other physical addresses are routed to the L3 port (Master 1) where they are decoded by the device infrastructure. The Cortex™-A8 memory map is shown in Table 3-30.

1. These addresses are decoded within the Cortex™-A8 subsystem.
2. These accesses occur through the DDR DMM TILER ports. The DDR DMM splits address ranges internally to address DDR EMIF and DDR DMM control registers based on DDR DMM tie-offs.
3. These addresses are routed to the Master 0 port for direct connection to the DDR DMM ELLA port.
4. DDR EMIF0 and DDR EMIF1 addresses may be contiguous or bank interleaved, depending on configuration of the DDR DMM.

3.9.5 C674x Memory Map

Because the C674x DSP has specific hardwired address decoding built in, the C674x memory map is slightly different than that of the Cortex™-A8. The C674x has a separate CFG bus which is used to access L4 peripherals and its UMAP1 bus has a direct connection into HDVICP2 SL2 (HDVICP2-0 and HDVICP2-1 only) memories. All C674x MDMA port accesses are routed through the System MMU for address translation.