SPRS614F March   2011  – March 2015 TMS320DM8165 , TMS320DM8167 , TMS320DM8168

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 ARM Subsystem
      1. 3.2.1 ARM Cortex-A8 RISC Processor
      2. 3.2.2 Embedded Trace Module (ETM)
      3. 3.2.3 ARM Cortex-A8 Interrupt Controller (AINTC)
      4. 3.2.4 System Interconnect
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 System Memory Management Unit (System MMU)
        1. 3.3.2.1 System MMU Registers
    4. 3.4 Media Controller
    5. 3.5 High-Definition Video Image Coprocessor 2 (HDVICP2)
    6. 3.6 Inter-Processor Communication
      1. 3.6.1 Mailbox Module
        1. 3.6.1.1 Mailbox Registers
      2. 3.6.2 Spinlock Module
        1. 3.6.2.1 Spinlock Registers
    7. 3.7 Power, Reset and Clock Management (PRCM) Module
    8. 3.8 SGX530 (DM8168 only)
    9. 3.9 Memory Map Summary
      1. 3.9.1 L3 Memory Map
      2. 3.9.2 L4 Memory Map
        1. 3.9.2.1 L4 Standard Peripheral
        2. 3.9.2.2 L4 High-Speed Peripheral
      3. 3.9.3 TILER Extended Addressing Map
      4. 3.9.4 Cortex™-A8 Memory Map
      5. 3.9.5 C674x Memory Map
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Assignments
      1. 4.1.1 Pin Map (Bottom View)
    2. 4.2 Terminal Functions
      1. 4.2.1  Boot Configuration
      2. 4.2.2  DDR2 and DDR3 Memory Controller Signals
      3. 4.2.3  Ethernet Media Access Controller (EMAC) Signals
      4. 4.2.4  General-Purpose Input/Output (GPIO) Signals
      5. 4.2.5  General-Purpose Memory Controller (GPMC) Signals
      6. 4.2.6  High-Definition Multimedia Interface (HDMI) Signals
      7. 4.2.7  Inter-Integrated Circuit (I2C) Signals
      8. 4.2.8  Multichannel Audio Serial Port Signals
      9. 4.2.9  Multichannel Buffered Serial Port Signals
      10. 4.2.10 Oscillator/Phase-Locked Loop (PLL) Signals
      11. 4.2.11 Peripheral Component Interconnect Express (PCIe) Signals
      12. 4.2.12 Reset, Interrupts, and JTAG Interface Signals
      13. 4.2.13 Secure Digital/Secure Digital Input Output (SD/SDIO) Signals
      14. 4.2.14 Serial ATA Signals
      15. 4.2.15 Serial Peripheral Digital Interconnect Format (SPI) Signals
      16. 4.2.16 Timer Signals
      17. 4.2.17 Universal Asynchronous Receiver/Transmitter (UART) Signals
      18. 4.2.18 Universal Serial Bus (USB) Signals
      19. 4.2.19 Video Input Signals
      20. 4.2.20 Digital Video Output Signals
      21. 4.2.21 Analog Video Output Signals
      22. 4.2.22 Reserved Pins
      23. 4.2.23 Supply Voltages
      24. 4.2.24 Ground Pins (VSS)
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (Unless Otherwise Noted)
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Resistance Characteristics
  6. 6 Device Configurations
    1. 6.1 Control Module
    2. 6.2 Revision Identification
    3. 6.3 Debugging Considerations
      1. 6.3.1 Pullup and Pulldown Resistors
    4. 6.4 Boot Sequence
      1. 6.4.1 Boot Mode Registers
    5. 6.5 Pin Multiplexing Control
      1. 6.5.1 PINCTRLx Register Descriptions
    6. 6.6 How to Handle Unused Pins
  7. 7 System Interconnect
    1. 7.1 L3 Interconnect
    2. 7.2 L4 Interconnect
  8. 8 Power, Reset, Clocking, and Interrupts
    1. 8.1 Power Supplies
      1. 8.1.1 Voltage and Power Domains
      2. 8.1.2 Power Domains
      3. 8.1.3 1-V AVS and 1-V Constant Power Domains
      4. 8.1.4 SmartReflex™
      5. 8.1.5 Memory Power Management
      6. 8.1.6 IO Power-Down Modes
      7. 8.1.7 Supply Sequencing
      8. 8.1.8 Power-Supply Decoupling
    2. 8.2 Reset
      1. 8.2.1  System-Level Reset Sources
      2. 8.2.2  Power-On Reset (POR pin)
      3. 8.2.3  External Warm Reset (RESET pin)
      4. 8.2.4  Emulation Warm Reset
      5. 8.2.5  Watchdog Reset
      6. 8.2.6  Software Global Cold Reset
      7. 8.2.7  Software Global Warm Reset
      8. 8.2.8  Test Reset (TRST pin)
      9. 8.2.9  Local Reset
      10. 8.2.10 Reset Priority
      11. 8.2.11 Reset Status Register
      12. 8.2.12 PCIe Reset Isolation
      13. 8.2.13 RSTOUT
      14. 8.2.14 Effect of Reset on Emulation and Trace
      15. 8.2.15 Reset During Power Domain Switching
      16. 8.2.16 Pin Behaviors at Reset
      17. 8.2.17 Reset Electrical Data and Timing
    3. 8.3 Clocking
      1. 8.3.1 Device Clock Inputs
        1. 8.3.1.1 Using the Internal Oscillators
      2. 8.3.2 SERDES_CLKN and SERDES_CLKP Input Clock
      3. 8.3.3 CLKIN32 Input Clock
      4. 8.3.4 PLLs
        1. 8.3.4.1 PLL Programming Limits
        2. 8.3.4.2 PLL Power Supply Filtering
        3. 8.3.4.3 PLL Locking Sequence
        4. 8.3.4.4 PLL Registers
      5. 8.3.5 SYSCLKs
      6. 8.3.6 Module Clocks
      7. 8.3.7 Output Clock Select Logic
    4. 8.4 Interrupts
      1. 8.4.1 Interrupt Summary List
      2. 8.4.2 Cortex™-A8 Interrupts
      3. 8.4.3 C674x Interrupts
  9. 9 Peripheral Information and Timings
    1. 9.1  Parameter Information
      1. 9.1.1 1.8-V and 3.3-V Signal Transition Levels
      2. 9.1.2 3.3-V Signal Transition Rates
      3. 9.1.3 Timing Parameters and Board Routing Analysis
    2. 9.2  Recommended Clock and Control Signal Transition Behavior
    3. 9.3  DDR2 and DDR3 Memory Controller
      1. 9.3.1 DDR2 Routing Specifications
        1. 9.3.1.1 Board Designs
        2. 9.3.1.2 DDR2 Interface
          1. 9.3.1.2.1  DDR2 Interface Schematic
          2. 9.3.1.2.2  Compatible JEDEC DDR2 Devices
          3. 9.3.1.2.3  PCB Stackup
          4. 9.3.1.2.4  Placement
          5. 9.3.1.2.5  DDR2 Keepout Region
          6. 9.3.1.2.6  Bulk Bypass Capacitors
          7. 9.3.1.2.7  High-Speed Bypass Capacitors
          8. 9.3.1.2.8  Net Classes
          9. 9.3.1.2.9  DDR2 Signal Termination
          10. 9.3.1.2.10 VREFSSTL_DDR Routing
        3. 9.3.1.3 DDR2 CK and ADDR_CTRL Routing
      2. 9.3.2 DDR3 Routing Specifications
        1. 9.3.2.1  Board Designs
          1. 9.3.2.1.1 DDR3 versus DDR2
        2. 9.3.2.2  DDR3 Device Combinations
          1. 9.3.2.2.1 DDR3 EMIFs
        3. 9.3.2.3  DDR3 Interface Schematic
          1. 9.3.2.3.1 32-Bit DDR3 Interface
          2. 9.3.2.3.2 16-Bit DDR3 Interface
        4. 9.3.2.4  Compatible JEDEC DDR3 Devices
        5. 9.3.2.5  PCB Stackup
        6. 9.3.2.6  Placement
        7. 9.3.2.7  DDR3 Keepout Region
        8. 9.3.2.8  Bulk Bypass Capacitors
        9. 9.3.2.9  High-Speed Bypass Capacitors
          1. 9.3.2.9.1 Return Current Bypass Capacitors
        10. 9.3.2.10 Net Classes
        11. 9.3.2.11 DDR3 Signal Termination
        12. 9.3.2.12 VREFSSTL_DDR Routing
        13. 9.3.2.13 VTT
        14. 9.3.2.14 CK and ADDR_CTRL Topologies and Routing Definition
          1. 9.3.2.14.1 Four DDR3 Devices
            1. 9.3.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 9.3.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 9.3.2.14.2 Two DDR3 Devices
            1. 9.3.2.14.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 9.3.2.14.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 9.3.2.14.3 One DDR3 Device
            1. 9.3.2.14.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 9.3.2.14.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
        15. 9.3.2.15 Data Topologies and Routing Definition
          1. 9.3.2.15.1 DQS, DQ and DM Topologies, Any Number of Allowed DDR3 Devices
          2. 9.3.2.15.2 DQS, DQ and DM Routing, Any Number of Allowed DDR3 Devices
        16. 9.3.2.16 Routing Specification
          1. 9.3.2.16.1 CK and ADDR_CTRL Routing Specification
          2. 9.3.2.16.2 DQS and DQ Routing Specification
      3. 9.3.3 DDR2 and DDR3 Memory Controller Register Descriptions
      4. 9.3.4 DDR2 and DDR3 PHY Register Descriptions
      5. 9.3.5 DDR2 and DDR3 Memory Controller Electrical Data and Timing
    4. 9.4  Emulation Features and Capability
      1. 9.4.1 Advanced Event Triggering (AET)
      2. 9.4.2 Trace
      3. 9.4.3 IEEE 1149.1 JTAG
        1. 9.4.3.1 JTAG ID (JTAGID) Register Description
        2. 9.4.3.2 JTAG Electrical Data and Timing
      4. 9.4.4 IEEE 1149.7 cJTAG
    5. 9.5  Enhanced Direct Memory Access (EDMA) Controller
      1. 9.5.1 EDMA Channel Synchronization Events
      2. 9.5.2 EDMA Peripheral Register Descriptions
    6. 9.6  Ethernet Media Access Controller (EMAC)
      1. 9.6.1 EMAC Peripheral Register Descriptions
      2. 9.6.2 EMAC Electrical Data and Timing
      3. 9.6.3 Management Data Input and Output (MDIO)
        1. 9.6.3.1 MDIO Peripheral Register Descriptions
        2. 9.6.3.2 MDIO Electrical Data and Timing
    7. 9.7  General-Purpose Input and Output (GPIO)
      1. 9.7.1 GPIO Peripheral Register Descriptions
      2. 9.7.2 GPIO Electrical Data and Timing
    8. 9.8  General-Purpose Memory Controller (GPMC) and Error Locator Module (ELM)
      1. 9.8.1 GPMC and ELM Peripheral Register Descriptions
      2. 9.8.2 GPMC Electrical Data and Timing
        1. 9.8.2.1 GPMC and NOR Flash Interface Synchronous Mode Timing
        2. 9.8.2.2 GPMC and NOR Flash Interface Asynchronous Mode Timing
        3. 9.8.2.3 GPMC and NAND Flash Interface Asynchronous Mode Timing
    9. 9.9  High-Definition Multimedia Interface (HDMI)
      1. 9.9.1 HDMI Interface Design Specifications
        1. 9.9.1.1 HDMI Interface Schematic
        2. 9.9.1.2 TMDS Routing
        3. 9.9.1.3 DDC Signals
        4. 9.9.1.4 HDMI ESD Protection Device (Required)
        5. 9.9.1.5 PCB Stackup Specifications
        6. 9.9.1.6 Grounding
      2. 9.9.2 HDMI Peripheral Register Descriptions
    10. 9.10 High-Definition Video Processing Subsystem (HDVPSS)
      1. 9.10.1 HDVPSS Electrical Data and Timing
      2. 9.10.2 Video DAC Guidelines and Electrical Data and Timing
    11. 9.11 Inter-Integrated Circuit (I2C)
      1. 9.11.1 I2C Peripheral Register Descriptions
      2. 9.11.2 I2C Electrical Data and Timing
    12. 9.12 Multichannel Audio Serial Port (McASP)
      1. 9.12.1 McASP Device-Specific Information
      2. 9.12.2 McASP0, McASP1, and McASP2 Peripheral Register Descriptions
      3. 9.12.3 McASP Electrical Data and Timing
    13. 9.13 Multichannel Buffered Serial Port (McBSP)
      1. 9.13.1 McBSP Peripheral Registers
      2. 9.13.2 McBSP Electrical Data and Timing
    14. 9.14 Peripheral Component Interconnect Express (PCIe)
      1. 9.14.1 PCIe Design and Layout Specifications
        1. 9.14.1.1 Clock Source
        2. 9.14.1.2 PCIe Connections and Interface Compliance
          1. 9.14.1.2.1 Coupling Capacitors
          2. 9.14.1.2.2 Polarity Inversion
          3. 9.14.1.2.3 Lane Reversal
        3. 9.14.1.3 Non-Standard PCIe Connections
          1. 9.14.1.3.1 PCB Stackup Specifications
          2. 9.14.1.3.2 Routing Specifications
      2. 9.14.2 PCIe Peripheral Register Descriptions
      3. 9.14.3 PCIe Electrical Data and Timing
    15. 9.15 Real-Time Clock (RTC)
      1. 9.15.1 RTC Register Descriptions
    16. 9.16 Secure Digital and Secure Digital Input Output (SD and SDIO)
      1. 9.16.1 SD and SDIO Peripheral Register Descriptions
      2. 9.16.2 SD and SDIO Electrical Data and Timing
        1. 9.16.2.1 SD Identification and Standard SD Mode
        2. 9.16.2.2 High-Speed SD Mode
    17. 9.17 Serial ATA Controller (SATA)
      1. 9.17.1 SATA Interface Design Specifications
        1. 9.17.1.1 SATA Interface Schematic
        2. 9.17.1.2 Compatible SATA Components and Modes
        3. 9.17.1.3 PCB Stackup Specifications
        4. 9.17.1.4 Routing Specifications
        5. 9.17.1.5 Coupling Capacitors
      2. 9.17.2 SATA Peripheral Register Descriptions
    18. 9.18 Serial Peripheral Interface (SPI)
      1. 9.18.1 SPI Peripheral Register Descriptions
      2. 9.18.2 SPI Electrical Data and Timing
    19. 9.19 Timers
      1. 9.19.1 Timer Peripheral Register Descriptions
      2. 9.19.2 Timer Electrical Data and Timing
    20. 9.20 Universal Asynchronous Receiver and Transmitter (UART)
      1. 9.20.1 UART Peripheral Register Descriptions
      2. 9.20.2 UART Electrical Data and Timing
    21. 9.21 Universal Serial Bus (USB2.0)
      1. 9.21.1 USB2.0 Peripheral Register Descriptions
      2. 9.21.2 USB2.0 Electrical Data and Timing
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
      2. 10.1.2 Device Speed Range Overview
    2. 10.2 Documentation Support
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CYG|1031
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Power, Reset, Clocking, and Interrupts

8.1 Power Supplies

8.1.1 Voltage and Power Domains

The device has the following voltage domains:

  • 1-V adaptive voltage scaling (AVS) domain - Main voltage domain for all modules
  • 1-V constant domain - Memories, PLLs, DACs, DDR IOs, HDMI, and USB PHYs
  • 1.8-V constant domain - PLLs, DACs, HDMI, and USB PHYs
  • 3.3-V constant domain - IOs and USB PHY
  • 1.5-V constant domain - DDR IOs, PCIe, and SATA SERDES
  • 0.9-V constant domain - USB PHY

These domains define groups of modules that share the same supply voltage for their core logic. Each voltage domain is powered by dedicated supply voltage rails. For the mapping between voltage domains and the supply pins associated with each, see Table 4-33.

Note: A regulated supply voltage must be supplied to each voltage domain at all times, regardless of the power domain states.

8.1.2 Power Domains

The device's 1-V AVS and 1-V constant voltage domains have seven power domains that supply power to both the core logic and SRAM within their associated modules. All other voltage domains have only always-on power domain.

Within the 1-V AVS and 1-V constant voltage domains, each power domain, except for the always-on domain, has an internal power switch that can completely remove power from that domain. At power-up, all domains, except always-on, come-up as power gated. Since there is an always-on domain in each voltage domain, all power supplies are expected to be ON all the time (as long as the device is in use).

For details on powering up or powering down the device power domains, see the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (SPRUGX8).

Note: All modules within a power domain are unavailable when the domain is powered OFF. For instructions on powering ON or powering OFF the domains, see the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (SPRUGX8).

8.1.3 1-V AVS and 1-V Constant Power Domains

  • HDVICP2-0 Domain

    • This power domain contains HDVICP2-0. If HDVICP2-0 is not used, it can be power gated.

  • HDVICP2-1 Domain

    • This power domain contains HDVICP2-1. If HDVICP2-1 is not used, it can be power gated.

  • HDVICP2-2 Domain

    • This power domain contains HDVICP2-2. If HDVICP2-2 is not used, it can be power gated.

    Note: Three HDVICP2 modules are available on the DM8168 and DM8167 devices and two HDVICP2 modules (HDVICP2-0 and HDVICP2-1) are available on the DM8165 devices.

  • Graphics Domain

    • This domain contains the SGX530 (available only on the DM8168 device).

  • Active Domain

    • The active domain has all modules that are only needed when the system is in "active" state. In any of the standby states, these modules are not needed. This domain contains the C674x DSP and HDVPSS peripheral.

  • Default Domain

    • The default domain contains modules that might be required even in standby mode. Having them in a separate power domain allows customers to power gate these modules when in standby mode. This domain has the DDR, SATA, PCIe, Media Controller and USB peripherals.

  • Always-On Domain

    • The always-on domain contains all modules that are required even when the system goes to standby mode. This includes the host ARM and modules that generate wake-up interrupts (for example, UART, RTC, GPIO, EMAC) as well as other low-power IOs.

8.1.4 SmartReflex™

The device contains SmartReflex modules that are required to minimize power consumption on the voltage domains using external variable-voltage power supplies. Based on the device process, temperature, and desired performance, the SmartReflex modules advise the host processor to raise or lower the supply voltage to each domain for minimal power consumption. The communication link between the host processor and the external regulators is a system-level decision and can be accomplished using GPIOs or I2C.

The major technique employed by SmartReflex in the device is adaptive voltage scaling (AVS). Based on the silicon process and temperature, the SmartReflex modules guide software in adjusting the core 1-V supply voltage within the desired range. This technique is called adaptive voltage scaling (AVS). AVS occurs continuously and in real time, helping to minimize power consumption in response to changing operating conditions.

NOTE

Implementation of SmartReflex AVS is required for proper device operation.

8.1.5 Memory Power Management

The device memories offer three different modes to save power when memories are not being used; Table 8-1 provides the details.

Table 8-1 Memory Power Management Modes

MODE POWER SAVING WAKE-UP LATENCY MEMORY CONTENTS
Light Sleep (LS) ~60% Low Preserved
Deep Sleep (DS) ~75% Medium Preserved
Shut Down (SD) ~95% High Lost

The device provides a feature that allows the software to put the chip-level memories (C674x L2, OCMC RAMs) in any of the three (LS, DS, and SD) modes. There are control registers in the control module to control the power-down state of C674x L2, OCMC RAM0, and OCMC RAM1. There are also status registers that can be used during power-up to check if memories are powered-up. For detailed instructions on entering and exiting from light sleep and deep sleep modes, see the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (SPRUGX8).

Memories inside switchable domains go to the shut down (SD) state whenever the power domain goes to the OFF state. Memories come back to functional state along with the domain power-up.

In order to reduce SRAM leakage, many SRAM blocks can be switched from active mode to shut-down mode. When SRAM is put in shut-down mode, the voltage supplied to it is automatically removed and all data in that SRAM is lost.

All SRAM located in a switchable power domain (all domains except always-on) automatically enters shut-down mode whenever its assigned associated power domain goes to the OFF state. The SRAM returns to the active state when the corresponding power domain returns to the ON state.

For detailed instructions on powering up or powering down the various device SRAM, see the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (SPRUGX8).

8.1.6 IO Power-Down Modes

The DDR3 IOs are put into power-down mode automatically when the default power domain is turned OFF.

The HDMI PHY controller is in the always-on power domain, so software must configure the PHY into power-down mode.

There is no power-down mode for the other 3.3-V IOs.

8.1.7 Supply Sequencing

The device power supplies must be sequenced in the following order:

  1. 3.3 V
  2. 1-V AVS
  3. 1-V Constant
  4. 1.8 V
  5. 1.5 V
  6. 0.9 V

Each supply (represented by VDDB in Figure 8-1) must begin actively ramping between 0 ms and 50 ms after the previous supply (represented by VDDA in Figure 8-1) in the sequence has reached 80% of its nominal value, as shown in Figure 8-1.

TMS320DM8168 TMS320DM8167 TMS320DM8165 pwr_seq_sprs614.gifFigure 8-1 Power Sequencing Requirements

NOTE

The device pins are not fail-safe. Device pins should not be externally driven before the corresponding supply rail has been powered up. The corresponding supply rail for each pin can be found in Section 4.2, Terminal Functions.

8.1.8 Power-Supply Decoupling

Recommended capacitors for power supply decoupling are all 0.1 µF in the smallest body size that can be used. Capacitors are more effective in the smallest physical size to limit lead inductance. For example, 0402 sized capacitors are better than 0603 sized capacitors, and so on.

Table 8-2 Recommended Power-Supply Decoupling Capacitors

SUPPLY MINIMUM CAPACITOR NO.
VDDA_PLL 2(1)
DVDD1P8 2
VDDT_SATA 2(1)
VDDT_PCIE 3(1)
CVDDC 20(2)
DVDD_3p3 64(2)
CVDD 28(2)
(1) PLL supplies benefit from filters or ferrite beads to keep the noise from causing clock jitter. The minimum recommendation is a ferrite bead with a resonance at 100 MHz along with at least one capacitor on the device side of the bead. Additional recommendation is to add one capacitor just before the bead to form a Pi filter. The filter needs to be as close as possible to the device pin, with the device-side capacitor being the most important component to be close to the device pin. PLL pins close together can be combined on the same supply. PLL pins spaced farther away from one another may need individual filtered supplies.
(2) It is recommended to have one bulk (15 µF or larger) capacitor for every 10 smaller capacitors placed as closely as possible to the device.

DDR-related supply capacitor numbers are provided in Section 9.3.

8.2 Reset

8.2.1 System-Level Reset Sources

The device has several types of system-level resets. Table 8-3 lists these reset types, along with the reset initiator and the effects of each reset on the device.

Table 8-3 System-Level Reset Types

TYPE INITIATOR RESETS ALL MODULES, EXCLUDING EMULATION RESETS EMULATION LATCHES BOOT PINS ASSERTS RSTOUT PIN
Power-On Reset (POR) POR pin Yes Yes Yes Yes
External Warm Reset RESET pin Yes No Yes Yes
Emulation Warm Reset On-Chip Emulation Logic Yes No No Yes
Watchdog Reset Watchdog Timer Yes No No Yes
Software Global Cold Reset Software Yes Yes No Yes
Software Global Warm Reset Software Yes No No Yes
Test Reset TRST pin No Yes No No

8.2.2 Power-On Reset (POR pin)

Power-on reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test and emulation logic. POR is also referred to as a cold reset since it is required to be asserted when the devices goes through a power-up cycle. However, a device power-up cycle is not required to initiate a power-on reset.

The following sequence must be followed during a power-on reset:

  1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted.
  2. Wait for the input clock sources SERDES_CLKN and SERDES_CLKNP to be stable (if used by the system) while keeping the POR pin asserted (low).
  3. Once the power supplies and the input clock source are stable, the POR pin must remain asserted (low) for a minimum of 32 DEV_MXI cycles. Within the low period of the POR pin, the following happens:
    1. All pins enter a Hi-Z mode.
    2. The PRCM asserts reset to all modules within the device.
    3. The PRCM begins propagating these clocks to the chip with the PLLs in bypass mode.
  4. The POR pin may now be deasserted (driven high). When the POR pin is deasserted (high):
    1. The BOOT pins are latched.
    2. Reset to the ARM Cortex-A8 is de-asserted, provided the processor clock is running.
    3. All other domain resets are released, provided the domain clocks are running.
    4. The clock, reset, and power-down state of each peripheral is determined by the default settings of the PRCM.
    5. The ARM Cortex-A8 begins executing from the default address (Boot ROM).

8.2.3 External Warm Reset (RESET pin)

An external warm reset is activated by driving the RESET pin active-low. This resets everything in the device, except the ARM Cortex-A8 interrupt controller, test, and emulation. An emulator session stays alive during warm reset.

The following sequence must be followed during a warm reset:

  1. Power supplies and input clock sources should already be stable.
  2. The RESET pin must be asserted (low) for a minimum of 32 DEV_MXI cycles. Within the low period of the RESET pin, the following happens:
    1. All pins, except test and emulation pins, enter a Hi-Z mode.
    2. The PRCM asserts reset to all modules within the device, except for the ARM Cortex-A8 interrupt controller, test, and emulation.
    3. RSTOUT is asserted.
  3. The RESET pin may now be de-asserted (driven high). When the RESET pin is de-asserted (high):
    1. The BOOT pins are latched.
    2. Reset to the ARM Cortex-A8 and modules without a local processor is de-asserted, with the exception of the ARM Cortex-A8 interrupt controller, test, and emulation.
    3. RSTOUT is de-asserted.
    4. The clock, reset, and power-down state of each peripheral is determined by the default settings of the PRCM.
    5. The ARM Cortex-A8 begins executing from the default address (Boot ROM).
    6. Since the ARM Cortex-A8 interrupt controller is not impacted by warm reset, application software needs to explicitly clear all pending interrupts in the ARM Cortex-A8 interrupt controller.

8.2.4 Emulation Warm Reset

An emulation warm reset is activated by the on-chip emulation module. It has the same effect and requirements as an external warm reset (RESET), with the exception that it does not re-latch the BOOT pins.

The emulator initiates an emulation warm reset via the ICEPick module. To invoke the emulation warm reset via the ICEPick module, the user can perform the following from the Code Composer Studio™ IDE menu:

Debug → Advanced Resets → System Reset.

8.2.5 Watchdog Reset

A watchdog reset is initiated when the watchdog timer counter reaches zero. It has the same effect and requirements as an external warm reset (RESET), with the exception that it does not re-latch the BOOT pins. In addition, a watchdog reset always results in RSTOUT being asserted.

8.2.6 Software Global Cold Reset

A software global cold reset is initiated under software control. It has the same effect and requirements as a power-on reset (POR), with the exception that it does not re-latch the BOOT pins.

Software initiates a software global cold reset by writing to RST_GLOBAL_COLD_SW in the PRM_RST_CTRL register.

8.2.7 Software Global Warm Reset

A software global warm reset is initiated under software control. It has the same effect and requirements as a external warm reset (RESET), with the exception that it does not re-latch the BOOT pins.

Software initiates a software global warm reset by writing to RST_GLOBAL_WARM_SW in the PRM_RST_CTRL register.

8.2.8 Test Reset (TRST pin)

A test reset is activated by the emulator asserting the TRST pin. The only effect of a test reset is to reset the emulation logic.

8.2.9 Local Reset

The local reset for various modules within the device is controlled by programming the PRCM and the module's internal registers. Only the associated module is reset when a local reset is asserted, leaving the rest of the device unaffected.

For details on local reset, see the PRCM chapter of the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (SPRUGX8) and individual subsystem and peripheral user's guides.

8.2.10 Reset Priority

If any of the above reset sources occur simultaneously, the device only processes the highest-priority reset request. The reset request priorities, from high to low, are as follows:

  1. Power-on reset (POR)
  2. Test reset (TRST)
  3. External warm reset (RESET)
  4. Emulation warm resets
  5. Watchdog reset
  6. Software global cold and warm resets.

8.2.11 Reset Status Register

The Reset Status Register (PRM_RSTST) contains information about the last reset that occurred in the system. For more information on this register, see the PRCM chapter of the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (SPRUGX8).

8.2.12 PCIe Reset Isolation

The device supports reset isolation for the PCI Express (PCIe) module. This means that the PCI Express subsystem can be reset without resetting the rest of the device.

When the device is a PCI Express Root Complex (RC), the PCIe subsystem can be reset by software through the PRCM. Software should ensure that there are no ongoing PCIe transactions before asserting this reset by first taking the PCIe subsystem into the IDLE state by programming the register CM_DEFAULT_PCI_CLKCTRL inside the PRCM. After bringing the PCIe subsystem out of reset, bus enumeration should be performed again and should treat all endpoints (EP) as if they had just been connected.

When the device is a PCI Express Endpoint (EP), the PCIe subsystem generates an interrupt when an in-band reset is received. Software should process this interrupt by putting the PCIe subsystem in the IDLE state and then asserting the PCIe local reset through the PRCM.

All device-level resets mentioned in the previous sections, except Test Reset, also reset the PCIe subsystem. Therefore, the device should issue a Hot Reset to all downstream devices and re-enumerate the bus upon coming out of reset.

8.2.13 RSTOUT

The RSTOUT pin on the device reflects device reset status and is de-asserted (high) when the device is out of reset. In addition, this output is always 3-stated and the internal pull resistor is disabled on this pin while POR or RESET is asserted; therefore, an external pullup or pulldown can be used to set the state of this pin (high or low) while POR or RESET is asserted. For more detailed information on external pullups and pulldowns, see Section 6.3.1. This output is always asserted low when any of the following resets occur:

  • Power-on reset (POR)
  • External warm reset
  • Emulation warm reset (RESET)
  • Software global cold or warm reset
  • Watchdog timer reset.

The RSTOUT pin remains asserted until PRCM releases the host ARM Cortex-A8 processor for reset.

8.2.14 Effect of Reset on Emulation and Trace

The device emulation and trace is only reset by the following sources:

  • Power-on reset (POR)
  • Software global cold reset
  • Test reset (TRST).

Other than these three, none of the other resets affect emulation and trace functionality.

8.2.15 Reset During Power Domain Switching

Each power domain has a dedicated warm reset and cold reset. Warm reset for a power domain is asserted under either of the following two conditions:

  1. A power-on reset, external warm reset, emulation warm reset, or software global cold or warm reset occurs.
  2. When that power domain switches from the ON state to the OFF state.

Cold reset for a power domain is asserted under either of the following two conditions:

  1. A power-on reset or software global cold reset occurs.
  2. When that power domain switches from the ON state to the OFF state.

8.2.16 Pin Behaviors at Reset

When any reset (other than test reset) described in Section 8.2.1 is asserted, all device pins are put into a Hi-Z state except for:

  • Emulation pins. These pins are only put into a Hi-Z state when POR or global software cold reset is asserted.
  • RSTOUT pin.

In addition, the PINCNTL registers, which control pin multiplexing, slew control, enabling the pullup or pulldown, and enabling the receiver, are reset to the default state. For a description of the RESET_ISO register, see the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (SPRUGX8).

Internal pullup or pulldown (IPU or IPD) resistors are enabled during and immediately after reset as described in the OTHER column in the tables in Section 4.2, Terminal Functions.

8.2.17 Reset Electrical Data and Timing

NOTE

If a configuration pin must be routed out from the device, the internal pullup or pulldown (IPU or IPD) resistor should not be relied upon; TI recommends the use of an external pullup or pulldown resistor.

Table 8-4 Timing Requirements for Reset

(see Figure 8-2 and Figure 8-3)
NO. MIN MAX UNIT
1 tw(RESET) Pulse duration, POR low or RESET low 32C(1) ns
2 tsu(CONFIG) Setup time, boot and configuration pins valid before POR high or RESET high(2) 12C(1) ns
3 th(CONFIG) Hold time, boot and configuration pins valid after POR high or RESET high(2) 0 ns
(1) C = 1/DEV_MXI clock frequency, in ns. The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET) requirement.
(2) For the list of boot and configuration pins, see Table 4-1, Boot Terminal Functions.

Table 8-5 Switching Characteristics Over Recommended Operating Conditions During Reset

(see Figure 8-2)
NO. PARAMETER MIN MAX UNIT
tw(RSTL) Pulse width, RESET low 10C(1) ns
4 td(RSTL_IORST) Delay time, RESET falling to all IO entering reset state 0 14 ns
5 td(RSTL_IOFUNC) Delay time, RESET rising to IO exiting reset state 0 14 ns
(1) C = 1/DEV_CLKIN clock frequency, in ns.
TMS320DM8168 TMS320DM8167 TMS320DM8165 td_reset_pwrup_SPRS614.gif
A. For more detailed information on the reset state of each pin, see Section 8.2.16, Pin Behaviors at Reset. For the IPU and IPD settings during reset, see Section 4.2, Terminal Functions.
Figure 8-2 Power-Up Timing
TMS320DM8168 TMS320DM8167 TMS320DM8165 td_reset_SPRS614.gif
A. For more detailed information on the reset state of each pin, see Section 8.2.16, Pin Behaviors at Reset. For the IPU and IPD settings during reset, see Section 4.2, Terminal Functions.
Figure 8-3 Warm Reset (RESET) Timing

8.3 Clocking

The device clocks are generated from several external reference clocks that are fed to on-chip PLLs and dividers (both inside and outside of the PRCM Module). Figure 8-4 shows a high-level overview of the device clocking structure. Note that to reduce complexity, all clocking connections are not shown. For detailed information on the device clocks, see the Device Clocking and Flying Adder PLL section of the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (SPRUGX8).

TMS320DM8168 TMS320DM8167 TMS320DM8165 sys_clk_ov_sprs614.gif
A. SGX530 is available only on the DM8168 device.
Figure 8-4 System Clocking Overview

8.3.1 Device Clock Inputs

The device has four on-chip PLLs and one reference clock which are generated by on-chip oscillators. In addition to the 27-MHz reference clock, a 100-MHz differential clock input is required for SATA and PCIe. A third clock input is an optional 32.768-kHz clock input (no on-chip oscillator) for the RTC.

The device clock input (DEV_MXI and DEV_CLKIN) is used to generate the majority of the internal reference clocks. An external square-wave clock can be supplied to DEV_CLKIN instead of using a crystal input. The device clock should be 27 MHz.

Section 8.3.1.1 provides details on using the on-chip oscillators with external crystals for the 27-MHz system oscillator.

8.3.1.1 Using the Internal Oscillators

When the internal oscillators are used to generate the device clock, external crystals are required to be connected across the MXI and MXO pins, along with two load capacitors, as shown in Figure 8-5. The external crystal load capacitors should also be connected to the associated oscillator ground pin (DEVOSC_VSS). The capacitors should not be connected to board ground (VSS).

TMS320DM8168 TMS320DM8167 TMS320DM8165 dev_osc_sprs614.gifFigure 8-5 27-MHz System Oscillator

The load capacitors, C1 and C2 in Figure 8-5, should be chosen such that the equation below is satisfied. CL in the equation is the load specified by the crystal manufacturer. Rd is an optional damping resistor. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator MXI, MXO, and VSS pins.

TMS320DM8168 TMS320DM8167 TMS320DM8165 eq1_osc_sprs614.gif

Table 8-6 Input Requirements for Crystal Circuit on the Device Oscillator

PARAMETER MIN NOM MAX UNIT
Start-up time (from power up until oscillating at stable frequency of 27 MHz) 4 ms
Crystal Oscillation frequency 27 MHz
Parallel Load Capacitance (C1 and C2) 12 24 pF
Crystal ESR 60 Ohm
Crystal Shunt Capacitance 5 pF
Crystal Oscillation Mode Fundamental Only
Crystal Frequency stability ±50 ppm

Table 8-7 DEV_CLKIN Clock Source Requirements(1)(2)(3)

(see Figure 8-6)
NO. MIN NOM MAX UNIT
1 tc(DCK) Cycle time, DEV_CLKIN 37.037 ns
2 tw(DCKH) Pulse duration, DEV_CLKIN high 0.45C 0.55C ns
3 tw(DCKL) Pulse duration, DEV_CLKIN low 0.45C 0.55C ns
4 tt(DCK) Transition time, DEV_CLKIN 7 ns
5 tJ(DCK) Period jitter, DEV_CLKIN (VDACs not used) 150 ps
Period jitter, DEV_CLKIN (VDACs used) A s
Sf Frequency stability, DEV_CLKIN ±50 ppm
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = DEV_CLKIN cycle time in ns.
(3)
TMS320DM8168 TMS320DM8167 TMS320DM8165 eq2_osc_sprs614.gif
Where SNR is the desired signal-to-noise ratio and BW is the highest DAC signal bandwidth used in the system (SD = 6 MHz, 720p or 1080i = 30 MHz, 1080p = 60 MHz).
TMS320DM8168 TMS320DM8167 TMS320DM8165 td_clkin_sprs614.gifFigure 8-6 DEV_CLKIN Timing

8.3.2 SERDES_CLKN and SERDES_CLKP Input Clock

A high-quality, low-jitter differential clock source is required for the PCIe and SATA PHYs. The clock is required to be AC coupled to the device's SERDES_CLKP and SERDES_CLKN pins according to the specifications in Table 8-11. Both the clock source and the coupling capacitors should be placed physically as close as possible to the processor.

When the PCIe interface is used, the SERDES_CLKN or SERDES_CLKP clock is required to meet the REFCLK AC specifications outlined in the PCI Express Card Electromechanical Specification (Gen.1 and Gen.2). When the SATA interface is used, the SERDES_CLKN or SERDES_CLKP clock is required to meet the specifications in Table 8-8. When both the PCIe and SATA interfaces are used, both sets of specifications must be met simultaneously.

Table 8-8 SERDES_CLKN and SERDES_CLKP Clock Source Requirements for SATA

PARAMETER MIN TYP MAX UNIT
Clock Frequency 100 MHz
Jitter 50 Ps pk-pk
Duty Cycle 40 60 %
Rise and Fall Time 700 ps

An HCSL differential clock source is required to meet the REFCLK AC specifications outlined in the PCI Express Card Electromechanical Specification, Rev. 2.0, at the input to the AC coupling capacitors. In addition, LVDS clock sources that are compliant to the above specification, but with the exceptions shown in Table 8-9, are also acceptable.

Table 8-9 Exceptions to REFCLK AC Specification for LVDS Clock Sources

SYMBOL PARAMETER MIN MAX UNIT
VIH Differential input high voltage (VIH) 125 1000 mV
VIL Differential input high voltage (VIL) -1000 -125 mV

Table 8-10 SERDES_CLKN and SERDES_CLKP Routing Specifications

PARAMETER MIN TYP MAX UNIT
Number of stubs allowed on SERDES_CLKN and SERDES_CLKP traces 0 Stubs
SERDES_CLKN and SERDES_CLKP trace length from oscillator to device 24000(1) Mils
SERDES_CLKN and SERDES_CLKP pair differential impedance 100 Ohms
Number of vias on each SERDES_CLKN and SERDES_CLKP trace(2) 3 Vias
SERDES_CLKN and SERDES_CLKP differential pair to any other trace spacing 2*DS(3)
(1) Keep trace length as short as possible.
(2) Vias must be used in pairs with their distance minimized.
(3) DS is the differential spacing of the SERDES_CLKN and SERDES_CLKP traces.

AC coupling capacitors are required on the SERDES_CLKN and SERDES_CLKP pair. Table 8-11 shows the requirements for these capacitors.

Table 8-11 SERDES_CLKN and SERDES_CLKP AC Coupling Capacitors Requirements

PARAMETER MIN TYP MAX UNIT
SERDES_CLKN and SERDES_CLKP AC coupling capacitor value(1) 0.24 0.27 4 nF
SERDES_CLKN and SERDES_CLKP AC coupling capacitor package size 0402 10 Mils(2)(3)
(1) The value of this capacitor depends on several factors including differential input clock swing. For a 100-MHz differential clock with an approximate 1-V voltage swing, the recommended typical value for the SERDES clock AC coupling capacitors is 270 pF. Deviating from this recommendation can result in the reduction of clock signal amplitude or lowering the noise rejection characteristics.
(2) LxW, 10 mil units; a 0402 is a 40x20 mil surface mount capacitor.
(3) The physical size of the capacitor should be as small as possible.

8.3.3 CLKIN32 Input Clock

An external 32.768-kHz clock input can optionally be provided at the CLKIN32 pin to serve as a reference clock in place of the RTCDIVIDER clock for the RTC and Timer modules. If the CLKIN32 pin is not connected to a 32.768-kHz clock input, this pin should be pulled low. The CLKIN32 source must meet the timing requirements shown in Table 8-12.

Table 8-12 Timing Requirements for CLKIN32(1)(2)

(see Figure 8-7)
NO. MIN NOM MAX UNIT
1 tc(CLKIN32) Cycle time, CLKIN32 1/32768 s
2 tw(CLKIN32H) Pulse duration, CLKIN32 high 0.45C 0.55C ns
3 tw(CKIN32L) Pulse duration, CLKIN32 low 0.45C 0.55C ns
4 tt(CLKIN32) Transition time, CLKIN32 7 ns
5 tJ(CLKIN32) Period jitter, CLKIN32 0.02C ns
(1) The reference points for the rise and fall transitions are measured at V IL MAX and V IH MIN.
(2) C = CLKIN32 cycle time, in ns. For example, when CLKIN32 frequency is 32768 Hz, use C = 1/32768 s.
TMS320DM8168 TMS320DM8167 TMS320DM8165 td_clkin32_prs647.gifFigure 8-7 CLKIN32 Timing

8.3.4 PLLs

The device contains four embedded PLLs (Main, Audio, Video and DDR) that provide clocks to different parts of the system. For a high-level view of the device clock architecture, including the PLL reference clock sources and connections, see Figure 8-4.

The reference clock for most of the PLLs comes from the DEV_CLKIN input clock. Also, each PLL supports a bypass mode in which the reference clock can be directly passed to the PLL CLKOUT. All device PLLs (except the DDR PLL) come-up in bypass mode after reset.

Flying-adder PLLs are used for all the on-chip PLLs. Figure 8-8 shows the basic structure of the flying-adder PLL.

TMS320DM8168 TMS320DM8167 TMS320DM8165 fly_add_pll_sprs614.gifFigure 8-8 Flying-Adder PLL

The flying-adder PLL has two main components: a multi-phase PLL and the flying-adder synthesizer. The multi-phase PLL takes an input reference clock (fr), multiplies it with factor, N, and provides a K-phase output to the flying-adder synthesizer. The flying-adder synthesizer takes this multi-phase clock input and produces a variable frequency clock (fs). There can be a post divider on this clock which takes in clock fs and drives out clock fo. The frequency of the clock driven out is given by:

TMS320DM8168 TMS320DM8167 TMS320DM8165 eq3_pll_sprs614.gif

There can be multiple flying-adder synthesizers attached to one multi-phase PLL to generate different frequencies. In this case, FREQ (4 bits of integer and 24 bits of fractional value) and M (1 to 255) values can be adjusted for each clock separately, based on the frequency needed. The multi-phase PLL used in this device has a value of K = 8.

For details on programming the device PLLs, see the PLL chapter of the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (SPRUGX8).

8.3.4.1 PLL Programming Limits

The PLL and Flying Adder Synthesizers support generation of a wide range of clocks that are all generated from the same input clock source. Therefore, these clocks are all synchronous. The flying-adder synthesizers take the multi-phase clock from the PLL and produce variable frequency clocks (fs) as stated in the previous section. Each variable frequency clock is then divided by a post divider before use.

The clock outputs from the PLL, Synthesizer and Post Divider contain period variations that must be considered. The minimum period of the generated clock is effectively the maximum clock rate. Different configurations of the PLL dividers, Synthesizer and output dividers will have larger or smaller amounts of phase variation. The equation below will calculate the minimum cycle period for a given set of settings. The result of the following minimum cycle equation must be greater than the value shown in Table 8-13.

The first term of the below equation is a characteristic of the Flying Adder PLL. The selection of M*FREQ is important. Choosing a non-integer value of M*FREQ will cause larger period variation and a higher peak instantaneous frequency. Use of non-integer M*FREQ can be done to create specific average frequencies at the cost of higher phase variation. Using integer values of M*FREQ result in minimum phase variation. The second and third terms are PLL phase jitter terms associated with the frequency synthesis. The second term is about 20ps and the third is normally 10ps.

Please refer to the Technical Reference Manual (SPRUGX8) for examples using this equation. The TRM also contains a standard set of configurations that we recommend for customer use.

TMS320DM8168 TMS320DM8167 TMS320DM8165 eq4_pll_sprs614.gif

Where:

  • PLL_CLKIN is the input clock frequency (in MHz) to the PLL before the P divider
  • Floor( ) = round down
  • M = PLL divider
  • FREQ = PLL frequency setting
  • A = 169 for all PLLs with the following exception: A = 218 for the audio PLL when its input is sourced from the main PLL output
  • H = 0 if M * FREQ is a multiple of 8; otherwise, H = 10
  • 800 MHz ≤ PLL_CLKIN * N / P ≤ 1600 MHz
  • 10 MHz ≤ PLL_CLKIN / P ≤ 60 MHz

Table 8-13 PLL Clock Frequencies(1)

CLOCK DEVICE SPEED RANGE MIN CYCLE (ps)
Main PLL
Clock 1 Blank 1250
2 1000
4 889
Clock 2 Blank 1000
2 833
4 741
Clock 3 Blank 1876
2 1667
4 1481
Clock 4 Blank 2000
2 1786
4 1667
DDR PLL
Clock 2 Blank, 2, 4 18519
Clock 3 Blank 2632
2 2632
4 2222
Video PLL
Clock 1 Blank, 2, 4 1515
Clock 2 Blank, 2, 4 1515
Clock 3 Blank, 2, 4 1515
Audio PLL
Clock 2 Blank, 2, 4 6329
Clock 3 Blank, 2, 4 5076
Clock 4 Blank, 2, 4 5076
Clock 5 Blank, 2, 4 5076
(1) For more information on the available device speed ranges for each part number, see Table 10-1

8.3.4.2 PLL Power Supply Filtering

The device PLLs are supplied externally via the VDDA_PLL power-supply pins. External filtering must be added on the PLL supply pins to ensure that the requirements in Table 8-14 are met.

Table 8-14 Power Supply Requirements

PARAMETER MIN MAX UNIT
Dynamic noise at VDDA_PLL pins 50 mV p-p

8.3.4.3 PLL Locking Sequence

All of the flying-adder PLLs (except the DDR PLL) come-up in bypass mode at reset. All of the registers (P, N, FREQ, and M) need to be programmed appropriately and then wait approximately 8 µs for PLL_Audio and 5 µs for the other PLLS to be locked. Verification that the PLL is locked can be checked by accessing the lock status bit in the PLL control register for each PLL (bit = 1 when the PLL is locked). Once the PLL is locked, then the FA-PLL can be taken out of bypass mode. Control for bypass mode is through chip-level registers. For more details on the PLL registers and bypass logic, see the PLL chapter of the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (SPRUGX8).

8.3.4.4 PLL Registers

The PLL control registers reside in the control module and are listed in Table 6-3.

8.3.5 SYSCLKs

In some cases, the system clock inputs and PLL outputs are sent to the PRCM module for division and multiplexing before being routed to the various device modules. These clock outputs from the PRCM module are called SYSCLKs. Table 8-15 lists the main device SYSCLKs along with their maximum supported clock frequencies. In addition, limits shown in the table may be further restricted by the clock frequency limitations of the device modules using these clocks. For more details on module clock frequency limits, see Section 8.3.6.

Table 8-15 SYSCLK Frequencies

SYSCLK PLL Type DEVICE SPEED RANGE(1) MAXIMUM FREQUENCY (MHz)(2) DESTINATION
SYSCLK1 Main Blank 750 To C674x DSP
2 930
4 1000
SYSCLK2 Main Blank 930 To ARM Cortex-A8
2 1100
4 1200
SYSCLK3 Main Blank 500 To HDVICP2s
2 550
4 630
SYSCLK4 Main Blank 460 L3, OCP clock for HDVPSS, TPTCs, TPCC, DMM, Unicache clock for Media Controller, EDMA
2 550
4 570
SYSCLK5 Main Blank 230 L3, L4_HS, OCP clock for EMAC, SATA, PCIe, Media Controller, OCMC RAM
2 275
4 285
SYSCLK6 Main Blank 115 L3, L4_STD, UART, I2C, SPI, SD, SDIO, TIMER, GPIO, PRCM, McASP, McBSP, GPMC, ELM, HDMI, WDT, Mailbox, RTC, Spinlock, SmartReflex and USB
2 137
4 143
SYSCLK7 Main Blank 90 Reserved
2 110
4 115
SYSCLK8 Main Blank 364 DMM, DDR OCP clock
2 364
4 425
SYSCLK9 DDR Blank, 2, 4 16 CEC clock, VTP
SYSCLK10 DDR Blank, 2, 4 48 SPI, I2C, SDIO, and UART functional clock
SYSCLK11 Video Blank, 2, 4 216 Reserved
SYSCLK13 Video Blank, 2, 4 165 HDVPSS
SYSCLK14 Video Blank, 2, 4 27 Reserved
SYSCLK15 Video Blank, 2, 4 165 HDVPSS
SYSCLK16 Video Blank, 2, 4 27 Reserved
SYSCLK17 Video Blank, 2, 4 54 HDVPSS
SYSCLK18 Audio Blank, 2, 4 32 KHz RTC
SYSCLK19 Audio Blank, 2, 4 160 Reserved
SYSCLK20 Audio Blank, 2, 4 196 Audio clock 1
SYSCLK21 Audio Blank, 2, 4 196 Audio clock 2
SYSCLK22 Audio Blank, 2, 4 196 Audio clock 3
SYSCLK23 Main Blank 310 SGX530 OCP clock
2 275
4 300
SYSCLK24 Main Blank, 2, 4 125 GMII clock
(1) For more information on the available device speed ranges for each part number, see Table 10-1.
(2) Maximum frequency must respect the minimum cycle limitations described in Section 8.3.4.1.

8.3.6 Module Clocks

Device modules receive their clock directly from an external clock input, directly from a PLL, or from a PRCM SYSCLK output. Table 8-16 lists the clock source options for each module, along with the maximum frequency that module can accept. The device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table to ensure proper module functionality.

Table 8-16 Module Clock Frequencies

MODULE CLOCK SOURCES DEVICE SPEED RANGE(1) MAX. FREQUENCY (MHz)(2)
C674x DSP SYSCLK1 Blank 750
2 930
4 1000
Cortex-A8 SYSCLK2 Blank 930
2 1100
4 1200
DMM SYSCLK4 Blank 460
2 550
4 570
DMM, DDR OCP SYSCLK8 Blank 364
2 364
4 425
EDMA SYSCLK4 Blank 460
2 550
4 570
ELM SYSCLK6 Blank 115
2 137
4 143
EMAC SYSCLK5 Blank 230
2 275
4 285
GPIO0 and GPIO1 SYSCLK6 Blank 115
2 137
4 143
SYSCLK18 Blank, 2, 4 32.768 KHz
GPMC SYSCLK6 Blank 115
2 137
4 143
HDMI SYSCLK6 Blank 115
2 137
4 143
HDMI CEC SYSCLK9 Blank, 2, 4 16
HDVICP2-0, HDVICP2-1, HDVICP2-2 SYSCLK3 Blank 500
2 550
4 630
HDVPSS VPDMA SYSCLK4 Blank 460
2 550
4 570
HDVPSS SYSCLK5 Blank 230
2 275
4 285
HDVPSS Interface SYSCLK6 Blank 115
2 137
4 143
HDVPSS HD VENCD SYSCLK13 Blank, 2, 4 165
HDVPSS HD VENCA SYSCLK15 Blank, 2, 4 165
HDVPSS SD VENC SYSCLK17 Blank, 2, 4 54
I2C0, I2C1 SYSCLK6 Blank 115
2 137
4 143
SYSCLK10 Blank, 2, 4 48
L3 SYSCLK4 Blank 460
2 550
4 570
L3 SYSCLK5 Blank 230
2 275
4 285
L3 SYSCLK6 Blank 115
2 137
4 143
L4 HS SYSCLK5 Blank 230
2 275
4 285
L4 STD SYSCLK6 Blank 115
2 137
4 143
Mailbox SYSCLK6 Blank 115
2 137
4 143
McASP0, McASP1, McASP2 SYSCLK6 Blank, 2, 4 125
McBSP SYSCLK6 Blank, 2, 4 125
Media Controller SYSCLK5 Blank 230
2 275
4 285
System MMU SYSCLK4 Blank 460
2 550
4 570
OCMC RAM SYSCLK5 Blank 230
2 275
4 285
PCIe SYSCLK5 Blank 230
2 275
4 285
RTC SYSCLK6 Blank 115
2 137
4 143
SYSCLK18 Blank, 2, 4 32.768 KHz
SATA SYSCLK5 Blank 230
2 275
4 285
SD, SDIO SYSCLK6 Blank 115
2 137
4 143
SYSCLK10 Blank, 2, 4 48
SGX530 SYSCLK23 Blank 310
2 275
4 300
SmartReflex SYSCLK6 Blank 115
2 137
4 143
SPI SYSCLK6 Blank 115
2 137
4 143
SYSCLK10 Blank, 2, 4 48
Spinlock SYSCLK6 Blank 115
2 137
4 143
Timers, WDT SYSCLK6 Blank 115
2 137
4 143
SYSCLK18 Blank, 2, 4 32.768 KHz
UART0, UART1, UART2 SYSCLK6 Blank 115
2 137
4 143
SYSCLK10 Blank, 2, 4 48
USB0, USB1 SYSCLK6 Blank 115
2 137
4 143
(1) For more information on the available device speed ranges for each part number, see Table 10-1.
(2) Maximum frequency must respect the minimum cycle limitations described in Section 8.3.4.1.

8.3.7 Output Clock Select Logic

The device includes one selectable general-purpose clock output (CLKOUT). The source for these output clocks is controlled by the CLKOUT_MUX register in the control module and shown in Figure 8-9.

TMS320DM8168 TMS320DM8167 TMS320DM8165 out_clk_sel_log_sprs614.gifFigure 8-9 CLKOUT Source Selection Logic

As shown in the figure, there are four possible sources for CLKOUT, one clock from each of the four PLLs. The selected clock can be further divided by any ratio from 1 to 1/8 before going out on the CLKOUT pin. The default selection is to select main PLL clock5, divider set to 1/1, and clock disabled.

Table 8-17 Switching Characteristics Over Recommended Operating Conditions for CLKOUT(1)(2)

(see Figure 8-10)
NO. PARAMETER MIN MAX UNIT
1 tc(CLKOUT) Cycle time, CLKOUT 10 ns
2 tw(CLKOUTH) Pulse duration, CLKOUT high 0.45P 0.55P ns
3 tw(CLKOUTL) Pulse duration, CLKOUT low 0.45P 0.55P ns
4 tt(CLKOUT) Transition time, CLKOUT 0.05P ns
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/CLKOUT clock frequency in nanoseconds (ns). For example, when CLKOUT frequency is 100 MHz, use P = 10 ns.
TMS320DM8168 TMS320DM8167 TMS320DM8165 td_clkout_sprs614.gifFigure 8-10 CLKOUT Timing

8.4 Interrupts

The device has a large number of interrupts. It also has masters (ARM Cortex™-A8, C674x DSP) capable of servicing interrupts. Specific details, such as the processing flow, configuration steps, and interrupt controller registers, for each of these masters are found in their respective subsystem documentation.

8.4.1 Interrupt Summary List

Table 8-18 lists all the device interrupts by module and indicates the interrupt destination: ARM Cortex™-A8, C674x DSP.

Table 8-18 Interrupts By Module

MODULE INTERRUPT DESTINATION DESCRIPTION
Cortex™-A8 C674x
HDVICP2-0(1) POMBINTRREQ0 Mailbox interrupt 0
POMBINTRPEND0 X
POMBINTRREQ1 Mailbox interrupt 1
POMBINTRPEND1 X
POMBINTRREQ2 Mailbox interrupt 2
POMBINTRPEND2
POSYNCINTRREQ0 iCONT1 sync interrupt
POSYNCINTRPEND0 X X
POSYNCINTRREQ1 iCONT2 sync interrupt
POSYNCINTRPEND1 X X
HDVICP2-1(1) POMBINTRREQ0 Mailbox interrupt 0
POMBINTRPEND0 X
POMBINTRREQ1 Mailbox interrupt 1
POMBINTRPEND1 X
POMBINTRREQ2 Mailbox interrupt 2
POMBINTRPEND2
POSYNCINTRREQ0 iCONT1 sync interrupt
POSYNCINTRPEND0 X X
POSYNCINTRREQ1 iCONT2 sync interrupt
POSYNCINTRPEND1 X X
HDVICP2-2(1) POMBINTRREQ0 Mailbox interrupt 0
POMBINTRPEND0 X
POMBINTRREQ1 Mailbox interrupt 1
POMBINTRPEND1 X
POMBINTRREQ2 Mailbox interrupt 2
POMBINTRPEND2
POSYNCINTRREQ0 iCONT1 sync interrupt
POSYNCINTRPEND0 X X
POSYNCINTRREQ1 iCONT2 sync interrupt
POSYNCINTRPEND1 X X
Serial ATA INTRQ SATA Module interrupt
INTRQ_PEND_N X
EMAC SS0 C0_RX_THRESH_INTR_REQ Receive threshold (non paced)
C0_RX_THRESH_INTR_PEND X X
C0_RX_INTR_REQ Receive pending interrupt (paced)
C0_RX_INTR_PEND X X
C0_TX_INTR_REQ Transmit pending interrupt (paced)
C0_TX_INTR_PEND X X
C0_MISC_INTR_REQ Stat, Host, MDIO LINKINT or MDIO USERINT
C0_MISC_INTR_PEND X X
EMAC SS1 C0_RX_THRESH_INTR_REQ Receive threshold (non paced)
C0_RX_THRESH_INTR_PEND X X
C0_RX_INTR_REQ Receive pending interrupt (paced)
C0_RX_INTR_PEND X X
C0_TX_INTR_REQ Transmit pending interrupt (paced)
C0_TX_INTR_PEND X X
C0_MISC_INTR_REQ Stat, Host, MDIO LINKINT or MDIO USERINT
C0_MISC_INTR_PEND X X
USB2.0 SS USBSS_INTR_REQ Queue MGR or CPPI Completion interrupt
USBSS_INTR_PEND X
USB0_INTR_REQ RX and TX DMA, Endpoint ready or error, or USB2.0 interrupt
USB0_INTR_PEND X
USB1_INTR_REQ
USB1_INTR_PEND X
SLV0P_SWAKEUP X USB wakeup
PCIe Gen2 PCIE_INT_I_INTR0 Legacy interrupt (RC mode only)
PCIE_INT_I_INTR_PEND_N0 X
PCIE_INT_I_INTR1 MSI interrupt (RC mode only)
PCIE_INT_I_INTR_PEND_N1 X
PCIE_INT_I_INTR2 Error interrupt
PCIE_INT_I_INTR_PEND_N2 X
PCIE_INT_I_INTR3 Power Management interrupt
PCIE_INT_I_INTR_PEND_N3 X
PCIE_INT_I_INTR4 Reserved
PCIE_INT_I_INTR_PEND_N4
PCIE_INT_I_INTR5
PCIE_INT_I_INTR_PEND_N5
PCIE_INT_I_INTR6
PCIE_INT_I_INTR_PEND_N6
PCIE_INT_I_INTR7
PCIE_INT_I_INTR_PEND_N7
PCIE_INT_I_INTR8
PCIE_INT_I_INTR_PEND_N8
PCIE_INT_I_INTR9
PCIE_INT_I_INTR_PEND_N9
PCIE_INT_I_INTR10
PCIE_INT_I_INTR_PEND_N10
PCIE_INT_I_INTR11
PCIE_INT_I_INTR_PEND_N11 X
PCIE_INT_I_INTR12
PCIE_INT_I_INTR_PEND_N12 X
PCIE_INT_I_INTR13
PCIE_INT_I_INTR_PEND_N13 X
PCIE_INT_I_INTR14
PCIE_INT_I_INTR_PEND_N14 X
PCIE_INT_I_INTR15
PCIE_INT_I_INTR_PEND_N15 X
SLE_IDLEP_SWAKEPUP X PCIe wakeup
TPCC TPCC_INT_PO[0] Region 0 DMA completion
TPCC_INT_PEND_N[0] X
TPCC_INT_PO[1] Region 1 DMA completion
TPCC_INT_PEND_N[1] X
TPCC_INT_PO[2] Region 2 DMA completion
TPCC_INT_PEND_N[2]
TPCC_INT_PO[3] Region 3 DMA completion
TPCC_INT_PEND_N[3]
TPCC_INT_PO[4] Region 4 DMA completion
TPCC_INT_PEND_N[4]
TPCC_INT_PO[5] Region 5 DMA completion
TPCC_INT_PEND_N[5]
TPCC_INT_PO[6] Region 6 DMA completion
TPCC_INT_PEND_N[6]
TPCC_INT_PO[7] Region 7 DMA completion
TPCC_INT_PEND_N[7]
TPCC_MPINT_PO Memory protection error
TPCC_MPINT_PEND_N X
TPCC_ERRINT_PO TPCC error
TPCC_ERRINT_PEND_N X X
TPCC_INTG_PO DMA Global completion
TPCC_INTG_PEND_N
TPTC 0 TPTC_ERRINT_PO TPTC0 error
TPTC_LERRINT_PO X X
TPTC_INT_PO TPTC0 completion
TPTC_LINT_PO
TPTC 1 TPTC_ERRINT_PO TPTC1 error
TPTC_LERRINT_PO X
TPTC_INT_PO TPTC1 completion
TPTC_LINT_PO
TPTC 2 TPTC_ERRINT_PO TPTC2 error
TPTC_LERRINT_PO X
TPTC_INT_PO TPTC2 completion
TPTC_LINT_PO
TPTC 3 TPTC_ERRINT_PO TPTC3 error
TPTC_LERRINT_PO X
TPTC_INT_PO TPTC3 completion
TPTC_LINT_PO
DDR EMIF4d 0 SYS_ERR_INTR EMIF error
SYS_ERR_INTR_PEND_N X
DDR EMIF4d 1 SYS_ERR_INTR
SYS_ERR_INTR_PEND_N X
GPMC GPMC_SINTERRUPT X GPMC interrupt
UART 0 NIRQ X X UART and IrDA 0 interrupt
UART 1 NIRQ X X UART and IrDA 1 interrupt
UART 2 NIRQ X X UART and IrDA 2 interrupt
Timer1 POINTR_REQ 32-bit Timer1 interrupt
POINTR_PEND X X
Timer2 POINTR_REQ 32-bit Timer2 interrupt
POINTR_PEND X X
Timer3 POINTR_REQ 32-bit Timer3 interrupt
POINTR_PEND X X
Timer4 POINTR_REQ 32-bit Timer4 interrupt
POINTR_PEND X X
Timer5 POINTR_REQ 32-bit Timer5 interrupt
POINTR_PEND X X
Timer6 POINTR_REQ 32-bit Timer6 interrupt
POINTR_PEND X X
Timer7 POINTR_REQ 32-bit Timer7 interrupt
POINTR_PEND X X
WDTimer1 PO_INT_REQ X X Watchdog Timer
I2C0 POINTRREQ I2C Bus interrupt
POINTRPEND X X
I2C1 POINTRREQ
POINTRPEND X X
SPI SINTERRUPTN X X SPI Interrupt
SDIO IRQOQN X X SDIO interrupt
McASP 0 MCASP_X_INTR_REQ McASP 0 Transmit interrupt
MCASP_X_INTR_PEND X X
MCASP_R_INTR_REQ McASP 0 Receive interrupt
MCASP_R_INTR_PEND X X
McASP 1 MCASP_X_INTR_REQ McASP 1 Transmit interrupt
MCASP_X_INTR_PEND X X
MCASP_R_INTR_REQ McASP 1 Receive interrupt
MCASP_R_INTR_PEND X X
McASP 2 MCASP_X_INTR_REQ McASP 2 Transmit interrupt
MCASP_X_INTR_PEND X X
MCASP_R_INTR_REQ McASP 2 Receive interrupt
MCASP_R_INTR_PEND X X
McBSP PORRINTERRUPT McBSP Receive Int (legacy mode)
PORXINTERRUPT McBSP Transmit Int (legacy mode)
PORROVFLINTERRUPT McBSP Receive Overflow Int (legacy mode)
PORCOMMONIRQ X X McBSP Common Int
RTC TIMER_INTR_REQ Timer interrupt
TIMER_INTR_PEND X
ALARM_INTR_REQ Alarm interrupt
ALARM_INTR_PEND X
GPIO 0 POINTRREQ1 GPIO 0 interrupt 1
POINTRPEND1 X X
POINTRREQ2 GPIO 0 interrupt 2
POINTRPEND2 X X
GPIO 1 POINTRREQ1 GPIO 1 interrupt 1
POINTRPEND1 X X
POINTRREQ2 GPIO 1 interrupt 2
POINTRPEND2 X X
PRCM Reserved
HDVPSS INTR0_INTR Intr0 pulse version
INTR0_INTR_PEND_N X Intr0 level version
INTR1_INTR Intr1 pulse version
INTR1_INTR_PEND_N X Intr1 level version
INTR2_INTR Intr2 pulse version
INTR2_INTR_PEND_N Intr2 level version
INTR3_INTR Intr3 pulse version
INTR3_INTR_PEND_N Intr3 level version
SGX530
(DM8168 only)		 THALIAIRQ X Error in the IMG bus
TARGETSINTERRUPT Target slave error interrupt
INITMINTERRUPT Initiator master error interrupt
HDMI 1.3 Transmit INTR0_INTR Intr0 pulse version
INTR0_INTR_PEND_N X X Intr0 level version
SmartReflex0 INTRREQ SVT SmartReflex interrupt pulse version
INTRPEND X SVT SmartReflex interrupt level version
SmartReflex1 INTRREQ HVT SmartReflex interrupt pulse version
INTRPEND X HVT SmartReflex interrupt level version
PBIST Reserved
Mailbox MAIL_U0_IRQ X Mailbox interrupt
MAIL_U1_IRQ X
MAIL_U2_IRQ
MAIL_U3_IRQ
NMI NMI_INT X NMI Interrupt
Infrastructure L3_DBG_IRQ X L3 debug error
L3_APP_IRQ X L3 application error
System MMU MMU_INTR X Table walk abort
DMM DMM_HIGH_INTRPEND X PAT fault
Cortex™-A8 SS COMMTX X ARM ICECrusher interrupt
COMMRX X
BENCH X ARM NPMUIRQ
ELM_IRQ X Error Location process completion
EMUINT X E2ICE interrupt
C674x
(Int Ctrl)		 EVT0 X C674x Internal
EVT1 X
EVT2 X
EVT3 X
INTERR X
C674x (ECM) EMU_DTDMA X
C674x (RTDX) EMU_RTDXRX X
EMU_RTDXTX X
C674x (EMC) IDMAINT0 X
IDMAINT1 X
EMC_IDMAERR X
C674x (PBIST) PBISTINT X
C674x (EFI A) EFIINTA X
C674x (EFI B) EFIINTB X
C674x (PMC) PMC_ED X
C674x (UMC) UMC_ED1 X
UMC_ED2 X
C674x (PDC) PDC_INT X
SYS SYS_CMPA X Sys
C674x (PMC) PMC_CMPA X C674x Internal
PMC_DMPA X
C674x (DMC) DMC_CMPA X
DMC_DMPA X
C674x (UMC) UMC_CMPA X
UMC_DMPA X
C674x (EMC) EMC_CMPA X
EMC_BUSERR X
(1) Three HDVICP2 modules are available on the DM8168 and DM8167 devices; two HDVICP2 modules (HDVICP2-0 and HDVICP2-1) are available on the DM8165 devices.

8.4.2 Cortex™-A8 Interrupts

The Cortex™-A8 Interrupt Controller (AINTC) takes ARM device interrupts and maps them to either the interrupt request (IRQ) or fast interrupt request (FIQ) of the ARM with an individual priority level. The AINTC interrupts must be active low-level interrupts.

The AINTC is responsible for prioritizing all service requests from the system peripherals directed to the Cortex™-A8 SS and generating either nIRQ or nFIQ to the host. The type of the interrupt (nIRQ or nFIQ) and the priority of the interrupt inputs are programmable. It has the capability to handle up to 128 requests which can be steered or prioritized as nFIQ or nIRQ interrupt requests.

The general features of the AINTC are:

  • Up to 128 level-sensitive interrupts inputs
  • Individual priority for each interrupt input
  • Each interrupt can be steered to nFIQ or nIRQ
  • Independent priority sorting for nFIQ and nIRQ.

Table 8-19 Cortex™-A8 Interrupt Controller Connections

INTERRUPT NUMBER ACRONYM SOURCE
0 EMUINT Internal
1 COMMTX Internal
2 COMMRX Internal
3 BENCH Internal
4 ELM_IRQ ELM
5-6 -
7 NMI External Pin
8 -
9 L3DEBUG L3
10 L3APPINT L3
11 -
12 EDMACOMPINT TPCC
13 EDMAMPERR TPCC
14 EDMAERRINT TPCC
15 -
16 SATAINT SATA
17 USBSSINT USBSS
18 USBINT0 USBSS
19 USBINT1 USBSS
20-33 -
34 USBWAKEUP USBSS
35 PCIeWAKEUP PCIe
36 DSSINT HDVPSS
37 GFXINT SGX530
(DM8168 only)
38 HDMIINT HDMI
39 -
40 MACRXTHR0 EMAC0
41 MACRXINT0 EMAC0
42 MACTXINT0 EMAC0
43 MACMISC0 EMAC0
44 MACRXTHR1 EMAC1
45 MACRXINT1 EMAC1
46 MACTXINT1 EMAC1
47 MACMISC1 EMAC1
48 PCIINT0 PCIe
49 PCIINT1 PCIe
50 PCIINT2 PCIe
51 PCIINT3 PCIe
52-63 -
64 SDINT SD, SDIO
65 SPIINT SPI
66 -
67 TINT1 Timer1
68 TINT2 Timer2
69 TINT3 Timer3
70 I2CINT0 I2C0
71 I2CINT1 I2C1
72 UARTINT0 UART0
73 UARTINT1 UART1
74 UARTINT2 UART2
75 RTCINT RTC
76 RTCALARMINT RTC
77 MBINT Mailbox
78-79 -
80 MCATXINT0 McASP0
81 MCARXINT0 McASP0
82 MCATXINT1 McASP1
83 MCARXINT1 McASP1
84 MCATXINT2 McASP2
85 MCARXINT2 McASP2
86 MCBSPINT McBSP
87-90 -
91 WDTINT WDTIMER1
92 TINT4 Timer4
93 TINT5 Timer5
94 TINT6 Timer6
95 TINT7 Timer7
96 GPIOINT0A GPIO 0
97 GPIOINT0B GPIO 0
98 GPIOINT1A GPIO 1
99 GPIOINT1B GPIO 1
100 GPMCINT GPMC
101 DDRERR0 DDR EMIF0
102 DDRERR1 DDR EMIF1
103 HDVICP0CONT1SYNC HDVICP2-0
104 HDVICP0CONT2SYNC HDVICP2-0
105 HDVICP1CONT1SYNC HDVICP2-1
106 HDVICP1CONT2SYNC HDVICP2-1
107 HDVICP0MBOXINT HDVICP2-0
108 HDVICP1MBOXINT HDVICP2-1
109 HDVICP2MBOXINT HDVICP2-2
110 HDVICP2CONT1SYNC HDVICP2-2
111 HDVICP2CONT2SYNC HDVICP2-2
112 TCERRINT0 TPTC0
113 TCERRINT1 TPTC1
114 TCERRINT2 TPTC2
115 TCERRINT3 TPTC3
116-119 -
120 SMRFLX0 SmartReflex0
121 SMRFLX1 SmartReflex1
122 SYSMMUINT System MMU
123 -
124 DMMINT DMM
125-127 -

8.4.3 C674x Interrupts

The C674x DSP interrupt controller is contained within the C674x module itself. This controller includes an event combiner, interrupt selector, exception combiner, and advanced event generator which allow a large number of system interrupts to be routed to its 12 maskable interrupts, grouped together for an exception input or used as an event trigger.

The controller combines device events into 12 CPU interrupts. It also controls the generation of the CPU exception and emulation interrupts and the generation of AEG events. The C674x interrupt controller captures all events on the rising-edge. (C674x interrupt inputs must be active high pulse interrupts.) On the device, only the level interrupts of the IP blocks are used and are converted into pulse interrupts by chip-level logic before connection to the C674x interrupt inputs.

Within the C674x interrupt controller, the interrupt selector contains registers that allow the user to program the source for each of 12 CPU interrupts. Some of the event sources come from within the C674x module itself.

Table 8-20 shows the connection of device interrupts to the C674x. Shaded entries are hard coded within the C674x module and cannot be changed.

Table 8-20 C674x Interrupt Controller Connections(1)

INTERRUPT NUMBER ACRONYM SOURCE
0 EVT0 C674x (INTC)
1 EVT1 C674x (INTC)
2 EVT2 C674x (INTC)
3 EVT3 C674x (INTC)
4-8 -
9 EMU_DTDMA C674x (ECM)
10 Reserved C674x
11 EMU_RTDXRX C674x (RTDX)
12 EMU_RTDXTX C674x (RTDX)
13 IDMAINT0 C674x (EMC)
14 IDMAINT1 C674x (EMC)
15 SDINT SD, SDIO
16 SPIINT SPI
17-19 -
20 EDMAINT TPCC
21 EDMAERRINT TPCC
22 TCERRINT0 TPTC0
23-31 -
32 MACRXTHR0 EMAC0
33 MACRXINT0 EMAC0
34 MACTXINT0 EMAC0
35 MACMISC0 EMAC0
36 MACRXTHR1 EMAC1
37 MACRXINT1 EMAC1
38 MACTXINT1 EMAC1
39 MACMISC1 EMAC1
40 DSSINT HDVPSS
41 HDMIINT HDMI
42-46 -
47 WDTINT WDTIMER1
48 -
49 TINT1 Timer1
50 TINT2 Timer2
51 TINT3 Timer3
52 TINT4 Timer4
53 TINT5 Timer5
54 TINT6 Timer6
55 TINT7 Timer7
56 MBINT Mailbox
57 -
58 I2CINT0 I2C0
59 I2CINT1 I2C1
60 UARTINT0 UART0
61 UARTINT1 UART1
62 UARTINT2 UART2
63 -
64 GPIOINT0A GPIO 0
65 GPIOINT0B GPIO 0
66 GPIOINT1A GPIO 1
67 GPIOINT1B GPIO 1
68-69 -
70 MCATXINT0 McASP0
71 MCARXINT0 McASP0
72 MCATXINT1 McASP1
73 MCARXINT1 McASP1
74 MCATXINT2 McASP2
75 MCARXINT2 McASP2
76 MCBSPINT McBSP
77-86 -
87 HDVICP2CONT1SYNC HDVICP2-2
88 HDVICP2CONT2SYNC HDVICP2-2
89 HDVICP2MBOXINT HDVICP2-2
90 HDVICP0CONT1SYNC HDVICP2-0
91 HDVICP0CONT2SYNC HDVICP2-0
92 HDVICP1CONT1SYNC HDVICP2-1
93 HDVICP1CONT2SYNC HDVICP2-1
94 HDVICP0MBOXINT HDVICP2-0
95 HDVICP1MBOXINT HDVICP2-1
96 INTERR C674x (INTC)
97 EMC_IDMAERR C674x (EMC)
98 PBISTINT C674x (PBIST)
99 Reserved C674x
100 EFIINTA C674x (EFI A)
101 EFIINTB C674x (EFI B)
102-112 Reserved C674x
113 PMC_ED C674x (PMC)
114-115 Reserved C674x
116 UMC_ED1 C674x (UMC)
117 UMC_ED2 C674x (UMC)
118 PDC_INT C674x (PDC)
119 SYS_CMPA SYS
120 PMC_CMPA C674x (PMC)
121 PMC_DMPA C674x (PMC)
122 DMC_CMPA C674x (DMC)
123 DMC_DMPA C674x (DMC)
124 UMC_CMPA C674x (UMC)
125 UMC_DMPA C674x (UMC)
126 EMC_CMPA C674x (EMC)
127 EMC_BUSERR C674x (EMC)
(1) Shaded interrupts are reserved for C674x internal use.