SPRS614F March   2011  – March 2015 TMS320DM8165 , TMS320DM8167 , TMS320DM8168

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 ARM Subsystem
      1. 3.2.1 ARM Cortex-A8 RISC Processor
      2. 3.2.2 Embedded Trace Module (ETM)
      3. 3.2.3 ARM Cortex-A8 Interrupt Controller (AINTC)
      4. 3.2.4 System Interconnect
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 System Memory Management Unit (System MMU)
        1. 3.3.2.1 System MMU Registers
    4. 3.4 Media Controller
    5. 3.5 High-Definition Video Image Coprocessor 2 (HDVICP2)
    6. 3.6 Inter-Processor Communication
      1. 3.6.1 Mailbox Module
        1. 3.6.1.1 Mailbox Registers
      2. 3.6.2 Spinlock Module
        1. 3.6.2.1 Spinlock Registers
    7. 3.7 Power, Reset and Clock Management (PRCM) Module
    8. 3.8 SGX530 (DM8168 only)
    9. 3.9 Memory Map Summary
      1. 3.9.1 L3 Memory Map
      2. 3.9.2 L4 Memory Map
        1. 3.9.2.1 L4 Standard Peripheral
        2. 3.9.2.2 L4 High-Speed Peripheral
      3. 3.9.3 TILER Extended Addressing Map
      4. 3.9.4 Cortex™-A8 Memory Map
      5. 3.9.5 C674x Memory Map
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Assignments
      1. 4.1.1 Pin Map (Bottom View)
    2. 4.2 Terminal Functions
      1. 4.2.1  Boot Configuration
      2. 4.2.2  DDR2 and DDR3 Memory Controller Signals
      3. 4.2.3  Ethernet Media Access Controller (EMAC) Signals
      4. 4.2.4  General-Purpose Input/Output (GPIO) Signals
      5. 4.2.5  General-Purpose Memory Controller (GPMC) Signals
      6. 4.2.6  High-Definition Multimedia Interface (HDMI) Signals
      7. 4.2.7  Inter-Integrated Circuit (I2C) Signals
      8. 4.2.8  Multichannel Audio Serial Port Signals
      9. 4.2.9  Multichannel Buffered Serial Port Signals
      10. 4.2.10 Oscillator/Phase-Locked Loop (PLL) Signals
      11. 4.2.11 Peripheral Component Interconnect Express (PCIe) Signals
      12. 4.2.12 Reset, Interrupts, and JTAG Interface Signals
      13. 4.2.13 Secure Digital/Secure Digital Input Output (SD/SDIO) Signals
      14. 4.2.14 Serial ATA Signals
      15. 4.2.15 Serial Peripheral Digital Interconnect Format (SPI) Signals
      16. 4.2.16 Timer Signals
      17. 4.2.17 Universal Asynchronous Receiver/Transmitter (UART) Signals
      18. 4.2.18 Universal Serial Bus (USB) Signals
      19. 4.2.19 Video Input Signals
      20. 4.2.20 Digital Video Output Signals
      21. 4.2.21 Analog Video Output Signals
      22. 4.2.22 Reserved Pins
      23. 4.2.23 Supply Voltages
      24. 4.2.24 Ground Pins (VSS)
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (Unless Otherwise Noted)
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Resistance Characteristics
  6. 6 Device Configurations
    1. 6.1 Control Module
    2. 6.2 Revision Identification
    3. 6.3 Debugging Considerations
      1. 6.3.1 Pullup and Pulldown Resistors
    4. 6.4 Boot Sequence
      1. 6.4.1 Boot Mode Registers
    5. 6.5 Pin Multiplexing Control
      1. 6.5.1 PINCTRLx Register Descriptions
    6. 6.6 How to Handle Unused Pins
  7. 7 System Interconnect
    1. 7.1 L3 Interconnect
    2. 7.2 L4 Interconnect
  8. 8 Power, Reset, Clocking, and Interrupts
    1. 8.1 Power Supplies
      1. 8.1.1 Voltage and Power Domains
      2. 8.1.2 Power Domains
      3. 8.1.3 1-V AVS and 1-V Constant Power Domains
      4. 8.1.4 SmartReflex™
      5. 8.1.5 Memory Power Management
      6. 8.1.6 IO Power-Down Modes
      7. 8.1.7 Supply Sequencing
      8. 8.1.8 Power-Supply Decoupling
    2. 8.2 Reset
      1. 8.2.1  System-Level Reset Sources
      2. 8.2.2  Power-On Reset (POR pin)
      3. 8.2.3  External Warm Reset (RESET pin)
      4. 8.2.4  Emulation Warm Reset
      5. 8.2.5  Watchdog Reset
      6. 8.2.6  Software Global Cold Reset
      7. 8.2.7  Software Global Warm Reset
      8. 8.2.8  Test Reset (TRST pin)
      9. 8.2.9  Local Reset
      10. 8.2.10 Reset Priority
      11. 8.2.11 Reset Status Register
      12. 8.2.12 PCIe Reset Isolation
      13. 8.2.13 RSTOUT
      14. 8.2.14 Effect of Reset on Emulation and Trace
      15. 8.2.15 Reset During Power Domain Switching
      16. 8.2.16 Pin Behaviors at Reset
      17. 8.2.17 Reset Electrical Data and Timing
    3. 8.3 Clocking
      1. 8.3.1 Device Clock Inputs
        1. 8.3.1.1 Using the Internal Oscillators
      2. 8.3.2 SERDES_CLKN and SERDES_CLKP Input Clock
      3. 8.3.3 CLKIN32 Input Clock
      4. 8.3.4 PLLs
        1. 8.3.4.1 PLL Programming Limits
        2. 8.3.4.2 PLL Power Supply Filtering
        3. 8.3.4.3 PLL Locking Sequence
        4. 8.3.4.4 PLL Registers
      5. 8.3.5 SYSCLKs
      6. 8.3.6 Module Clocks
      7. 8.3.7 Output Clock Select Logic
    4. 8.4 Interrupts
      1. 8.4.1 Interrupt Summary List
      2. 8.4.2 Cortex™-A8 Interrupts
      3. 8.4.3 C674x Interrupts
  9. 9 Peripheral Information and Timings
    1. 9.1  Parameter Information
      1. 9.1.1 1.8-V and 3.3-V Signal Transition Levels
      2. 9.1.2 3.3-V Signal Transition Rates
      3. 9.1.3 Timing Parameters and Board Routing Analysis
    2. 9.2  Recommended Clock and Control Signal Transition Behavior
    3. 9.3  DDR2 and DDR3 Memory Controller
      1. 9.3.1 DDR2 Routing Specifications
        1. 9.3.1.1 Board Designs
        2. 9.3.1.2 DDR2 Interface
          1. 9.3.1.2.1  DDR2 Interface Schematic
          2. 9.3.1.2.2  Compatible JEDEC DDR2 Devices
          3. 9.3.1.2.3  PCB Stackup
          4. 9.3.1.2.4  Placement
          5. 9.3.1.2.5  DDR2 Keepout Region
          6. 9.3.1.2.6  Bulk Bypass Capacitors
          7. 9.3.1.2.7  High-Speed Bypass Capacitors
          8. 9.3.1.2.8  Net Classes
          9. 9.3.1.2.9  DDR2 Signal Termination
          10. 9.3.1.2.10 VREFSSTL_DDR Routing
        3. 9.3.1.3 DDR2 CK and ADDR_CTRL Routing
      2. 9.3.2 DDR3 Routing Specifications
        1. 9.3.2.1  Board Designs
          1. 9.3.2.1.1 DDR3 versus DDR2
        2. 9.3.2.2  DDR3 Device Combinations
          1. 9.3.2.2.1 DDR3 EMIFs
        3. 9.3.2.3  DDR3 Interface Schematic
          1. 9.3.2.3.1 32-Bit DDR3 Interface
          2. 9.3.2.3.2 16-Bit DDR3 Interface
        4. 9.3.2.4  Compatible JEDEC DDR3 Devices
        5. 9.3.2.5  PCB Stackup
        6. 9.3.2.6  Placement
        7. 9.3.2.7  DDR3 Keepout Region
        8. 9.3.2.8  Bulk Bypass Capacitors
        9. 9.3.2.9  High-Speed Bypass Capacitors
          1. 9.3.2.9.1 Return Current Bypass Capacitors
        10. 9.3.2.10 Net Classes
        11. 9.3.2.11 DDR3 Signal Termination
        12. 9.3.2.12 VREFSSTL_DDR Routing
        13. 9.3.2.13 VTT
        14. 9.3.2.14 CK and ADDR_CTRL Topologies and Routing Definition
          1. 9.3.2.14.1 Four DDR3 Devices
            1. 9.3.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 9.3.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 9.3.2.14.2 Two DDR3 Devices
            1. 9.3.2.14.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 9.3.2.14.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 9.3.2.14.3 One DDR3 Device
            1. 9.3.2.14.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 9.3.2.14.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
        15. 9.3.2.15 Data Topologies and Routing Definition
          1. 9.3.2.15.1 DQS, DQ and DM Topologies, Any Number of Allowed DDR3 Devices
          2. 9.3.2.15.2 DQS, DQ and DM Routing, Any Number of Allowed DDR3 Devices
        16. 9.3.2.16 Routing Specification
          1. 9.3.2.16.1 CK and ADDR_CTRL Routing Specification
          2. 9.3.2.16.2 DQS and DQ Routing Specification
      3. 9.3.3 DDR2 and DDR3 Memory Controller Register Descriptions
      4. 9.3.4 DDR2 and DDR3 PHY Register Descriptions
      5. 9.3.5 DDR2 and DDR3 Memory Controller Electrical Data and Timing
    4. 9.4  Emulation Features and Capability
      1. 9.4.1 Advanced Event Triggering (AET)
      2. 9.4.2 Trace
      3. 9.4.3 IEEE 1149.1 JTAG
        1. 9.4.3.1 JTAG ID (JTAGID) Register Description
        2. 9.4.3.2 JTAG Electrical Data and Timing
      4. 9.4.4 IEEE 1149.7 cJTAG
    5. 9.5  Enhanced Direct Memory Access (EDMA) Controller
      1. 9.5.1 EDMA Channel Synchronization Events
      2. 9.5.2 EDMA Peripheral Register Descriptions
    6. 9.6  Ethernet Media Access Controller (EMAC)
      1. 9.6.1 EMAC Peripheral Register Descriptions
      2. 9.6.2 EMAC Electrical Data and Timing
      3. 9.6.3 Management Data Input and Output (MDIO)
        1. 9.6.3.1 MDIO Peripheral Register Descriptions
        2. 9.6.3.2 MDIO Electrical Data and Timing
    7. 9.7  General-Purpose Input and Output (GPIO)
      1. 9.7.1 GPIO Peripheral Register Descriptions
      2. 9.7.2 GPIO Electrical Data and Timing
    8. 9.8  General-Purpose Memory Controller (GPMC) and Error Locator Module (ELM)
      1. 9.8.1 GPMC and ELM Peripheral Register Descriptions
      2. 9.8.2 GPMC Electrical Data and Timing
        1. 9.8.2.1 GPMC and NOR Flash Interface Synchronous Mode Timing
        2. 9.8.2.2 GPMC and NOR Flash Interface Asynchronous Mode Timing
        3. 9.8.2.3 GPMC and NAND Flash Interface Asynchronous Mode Timing
    9. 9.9  High-Definition Multimedia Interface (HDMI)
      1. 9.9.1 HDMI Interface Design Specifications
        1. 9.9.1.1 HDMI Interface Schematic
        2. 9.9.1.2 TMDS Routing
        3. 9.9.1.3 DDC Signals
        4. 9.9.1.4 HDMI ESD Protection Device (Required)
        5. 9.9.1.5 PCB Stackup Specifications
        6. 9.9.1.6 Grounding
      2. 9.9.2 HDMI Peripheral Register Descriptions
    10. 9.10 High-Definition Video Processing Subsystem (HDVPSS)
      1. 9.10.1 HDVPSS Electrical Data and Timing
      2. 9.10.2 Video DAC Guidelines and Electrical Data and Timing
    11. 9.11 Inter-Integrated Circuit (I2C)
      1. 9.11.1 I2C Peripheral Register Descriptions
      2. 9.11.2 I2C Electrical Data and Timing
    12. 9.12 Multichannel Audio Serial Port (McASP)
      1. 9.12.1 McASP Device-Specific Information
      2. 9.12.2 McASP0, McASP1, and McASP2 Peripheral Register Descriptions
      3. 9.12.3 McASP Electrical Data and Timing
    13. 9.13 Multichannel Buffered Serial Port (McBSP)
      1. 9.13.1 McBSP Peripheral Registers
      2. 9.13.2 McBSP Electrical Data and Timing
    14. 9.14 Peripheral Component Interconnect Express (PCIe)
      1. 9.14.1 PCIe Design and Layout Specifications
        1. 9.14.1.1 Clock Source
        2. 9.14.1.2 PCIe Connections and Interface Compliance
          1. 9.14.1.2.1 Coupling Capacitors
          2. 9.14.1.2.2 Polarity Inversion
          3. 9.14.1.2.3 Lane Reversal
        3. 9.14.1.3 Non-Standard PCIe Connections
          1. 9.14.1.3.1 PCB Stackup Specifications
          2. 9.14.1.3.2 Routing Specifications
      2. 9.14.2 PCIe Peripheral Register Descriptions
      3. 9.14.3 PCIe Electrical Data and Timing
    15. 9.15 Real-Time Clock (RTC)
      1. 9.15.1 RTC Register Descriptions
    16. 9.16 Secure Digital and Secure Digital Input Output (SD and SDIO)
      1. 9.16.1 SD and SDIO Peripheral Register Descriptions
      2. 9.16.2 SD and SDIO Electrical Data and Timing
        1. 9.16.2.1 SD Identification and Standard SD Mode
        2. 9.16.2.2 High-Speed SD Mode
    17. 9.17 Serial ATA Controller (SATA)
      1. 9.17.1 SATA Interface Design Specifications
        1. 9.17.1.1 SATA Interface Schematic
        2. 9.17.1.2 Compatible SATA Components and Modes
        3. 9.17.1.3 PCB Stackup Specifications
        4. 9.17.1.4 Routing Specifications
        5. 9.17.1.5 Coupling Capacitors
      2. 9.17.2 SATA Peripheral Register Descriptions
    18. 9.18 Serial Peripheral Interface (SPI)
      1. 9.18.1 SPI Peripheral Register Descriptions
      2. 9.18.2 SPI Electrical Data and Timing
    19. 9.19 Timers
      1. 9.19.1 Timer Peripheral Register Descriptions
      2. 9.19.2 Timer Electrical Data and Timing
    20. 9.20 Universal Asynchronous Receiver and Transmitter (UART)
      1. 9.20.1 UART Peripheral Register Descriptions
      2. 9.20.2 UART Electrical Data and Timing
    21. 9.21 Universal Serial Bus (USB2.0)
      1. 9.21.1 USB2.0 Peripheral Register Descriptions
      2. 9.21.2 USB2.0 Electrical Data and Timing
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
      2. 10.1.2 Device Speed Range Overview
    2. 10.2 Documentation Support
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CYG|1031
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Device Configurations

6.1 Control Module

The device control module includes status and control logic not addressed within the peripherals or the remainder of the device infrastructure. This module is the primary point of control for the following areas of the device:

  • Functional IO multiplexing
  • Device status
  • Static device configuration
  • Open-core protocol (OCP) interface for standard and customer programmable e-Fuse bit shift registers.

The control module primarily implements a bank of registers accessible (read and write) by the software along with some read-only registers carrying status information. Most register bits are exported as control signals for other logic blocks on the device. Certain control module registers have default values based upon the device type as decoded from e-Fuse.

The read and write registers can be divided into the following classes:

  • Static device configuration registers
  • Status and configuration registers
  • Boot registers

Table 6-1 shows the general register groupings and Table 6-2 through Table 6-4 provide register summaries for each group.

Table 6-1 Control Module Register Map

ADDRESS OFFSET REGISTER GROUP SEE
0x0000 - 0x0020 OCP Configuration registers Table 6-2
0x0024 - 0x003C Reserved
0x0040 – 0x00FC Device Boot registers Table 6-7
0x0300 - 0x03FC Reserved
0x0400 - 0x05FC PLL Control registers Table 6-3
0x0600 - 0x07FC Device Configuration registers Table 6-4
0x0800 - 0x0FFC PAD Control registers Section 6.5

Table 6-2 OCP Configuration Registers Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4814 0000 CONTROL_REVISION Control module Revision number
0x4814 0004 - 0x4814 000C - Reserved
0x4814 0010 CONTROL_SYSCONFIG Idle mode parameters
0x4814 0014 - 0x4814 003C - Reserved

Table 6-3 PLL Control Registers Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4814 0400 MAINPLL_CTRL Main PLL base frequency control
0x4814 0404 MAINPLL_PWD Main PLL clock output powerdown
0x4814 0408 MAINPLL_FREQ1 Main Clock 1 fractional divider
0x4814 040C MAINPLL_DIV1 Main Clock 1 post divider
0x4814 0410 MAINPLL_FREQ2 Main Clock 2 fractional divider
0x4814 0414 MAINPLL_DIV2 Main Clock 2 post divider
0x4814 0418 MAINPLL_FREQ3 Main Clock 3 fractional divider
0x4814 041C MAINPLL_DIV3 Main Clock 3 post divider
0x4814 0420 MAINPLL_FREQ4 Main Clock 4 fractional divider
0x4814 0424 MAINPLL_DIV4 Main Clock 4 post divider
0x4814 0428 MAINPLL_FREQ5 Main Clock 5 fractional divider
0x4814 042C MAINPLL_DIV5 Main Clock 5 post divider
0x4814 0430 - Reserved
0x4814 0434 MAINPLL_DIV6 Main Clock 6 post divider
0x4814 0438 - Reserved
0x4814 043C MAINPLL_DIV7 Main Clock 7 post divider
0x4814 0440 DDRPLL_CTRL DDR PLL base frequency control
0x4814 0444 DDRPLL_PWD DDR PLL clock output powerdown
0x4814 0448 - Reserved
0x4814 044C DDR_PLL_DIV1 DDR Clock 1 post divider
0x4814 0450 DDRPLL_FREQ2 DDR Clock 2 fractional divider
0x4814 0454 DDR_PLL_DIV2 DDR Clock 2 post divider
0x4814 0458 DDRPLL_FREQ3 DDR Clock 3 fractional divider
0x4814 045C DDR_PLL_DIV3 DDR Clock 3 post divider
0x4814 0460 DDRPLL_FREQ4 DDR Clock 4 fractional divider
0x4814 0464 DDR_PLL_DIV4 DDR Clock 4 post divider
0x4814 0468 DDRPLL_FREQ5 DDR Clock 5 fractional divider
0x4814 046C DDR_PLL_DIV5 DDR Clock 5 post divider
0x4814 0470 VIDEOPLL_CTRL Video PLL base frequency control
0x4814 0474 VIDEOPLL_PWD Video PLL clock output powerdown
0x4814 0478 VIDEOPLL_FREQ1 Video Clock 1 fractional divider
0x4814 047C VIDEOPLL_DIV1 Video Clock 1 post divider
0x4814 0480 VIDEOPLL_FREQ2 Video Clock 2 fractional divider
0x4814 0484 VIDEOPLL_DIV2 Video Clock 2 post divider
0x4814 0488 VIDEOPLL_FREQ3 Video Clock 3 fractional divider
0x4814 048C VIDEOPLL_DIV3 Video Clock 3 post divider
0x4814 0490 - 0x4814 049C - Reserved
0x4814 04A0 AUDIOPLL_CTRL Audio PLL base frequency control
0x4814 04A4 AUDIOPLL_PWD Audio PLL clock output powerdown
0x4814 04A8 - Reserved
0x4814 04AC - Reserved
0x4814 04B0 AUDIOPLL_FREQ2 Audio Clock 2 fractional divider
0x4814 04B4 AUDIOPLL_DIV2 Audio Clock 2 post divider
0x4814 04B8 AUDIOPLL_FREQ3 Audio Clock 3 fractional divider
0x4814 04BC AUDIOPLL_DIV3 Audio Clock 3 post divider
0x4814 04C0 AUDIOPLL_FREQ4 Audio Clock 4 fractional divider
0x4814 04C4 AUDIOPLL_DIV4 Audio Clock 4 post divider
0x4814 04C8 AUDIOPLL_FREQ5 Audio Clock 5 fractional divider
0x4814 04CC AUDIOPLL_DIV5 Audio Clock 5 post divider
0x4814 04D0 - 0x4814 05FC - Reserved

Table 6-4 Device Configuration Registers Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4814 0600 DEVICE_ID Device Identification
0x4814 0604 - Reserved
0x4814 0608 INIT_PRESSURE_0 L3 Initiator Pressure
0x4814 060C INIT_PRESSURE_1 L3 Initiator Pressure
0x4814 0610 MMU_CFG System MMU Configuration
0x4814 0614 TPTC_CFG Transfer Controller Configuration
0x4814 0618 DDR_CTRL DDR Interface Control
0x4814 061C DSP_IDLE_CFG DSP Standby and Idle Management Configuration
0x4814 0620 USB_CTRL USB Control
0x4814 0624 USBPHY_CTRL0 USB0 Phy Control
0x4814 0628 - Reserved
0x4814 062C USBPHY_CTRL1 USB1 Phy Control
0x4814 0630 MAC_ID0_LO Ethernet MAC Address 0
0x4814 0634 MAC_ID0_HI Ethernet MAC Address 0
0x4814 0638 MAC_ID1_LO Ethernet MAC Address 1
0x4814 063C MAC_ID1_HI Ethernet MAC Address 1
0x4814 0640 PCIE_CFG PCIe Module Configuration
0x4814 0644 - Reserved
0x4814 0648 CLK_CTRL Input Oscillator Control
0x4814 064C AUDIO_CTRL Audio Control
0x4814 0650 DSPMEM_SLEEP DSP Memory Sleep Mode Configuration
0x4814 0654 OCMEM_SLEEP On-Chip Memory Sleep Mode Configuration
0x4814 0658 - 0x4814 065C - Reserved
0x4814 0660 HD_DAC_CTRL HD DAC Control
0x4814 0664 HD_DACA_CAL HD DAC A Calibration
0x4814 0668 HD_DACB_CAL HD DAC B Calibration
0x4814 066C HD_DACC_CAL HD DAC C Calibration
0x4814 0670 SD_DAC_CTRL SD DAC Control
0x4814 0674 SD_DACA_CAL SD DAC A Calibration
0x4814 0678 SD_DACB_CAL SD DAC B Calibration
0x4814 067C SD_DACC_CAL SD DAC C Calibration
0x4814 0680 SD_DACD_CAL SD DAC D Calibration
0x4814 0684 - 0x4814 0688 - Reserved
0x4814 068C BANDGAP_CTRL DAC Band-gap Control
0x4814 0690 HW_EVT_SEL_GRP1 System Trace Hardware Event Select Group 1
0x4814 0694 HW_EVT_SEL_GRP2 System Trace Hardware Event Select Group 2
0x4814 0698 HW_EVT_SEL_GRP3 System Trace Hardware Event Select Group 3
0x4814 069C HW_EVT_SEL_GRP4 System Trace Hardware Event Select Group 4
0x4814 06A0 - 0x4814 06F4 - Reserved
0x4814 06F8 HDMI_OBSCLK_CTRL HDMI Observe Clock Control
0x4814 06FC SERDES_CTRL Serdes Control
0x4814 0700 UCB_CLK_CTL USB Clock Control
0x4814 0704 PLL_OBSCLK_CTRL PLL Observe Clock Control
0x4814 0708 - Reserved
0x4814 070C DDR_RCD RCD Power Enable or Disable
0x4814 0710 - 0x4814 07FC - Reserved

6.2 Revision Identification

The silicon revision can be read in the DEVREV bit field value of the device identification (DEVICE_ID) register (located at 0x4814 0600). The DEVREV field of the DEVICE_ID register changes between silicon revisions. Table 6-5 lists the contents of the device revision (DEVREV) field value for each revision of the device.

Table 6-5 Device Revision (DEVREV) Bit Field Value

SILICON REVISION DEVICE REVISION FIELD VALUE
DEVREV[31:28]
2.1 0011
2.0 0010
1.1 0001
1.0 0000

More details on the DEVICE_ID register can be found in the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (literature number SPRUGX8).

6.3 Debugging Considerations

6.3.1 Pullup and Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup and pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup or pulldown resistors.

An external pullup or pulldown resistor needs to be used in the following situations:

  • Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external pullup or pulldown resistor is strongly recommended, even if the IPU or IPD matches the desired value or state.
  • Other Input Pins: If the IPU or IPD does not match the desired value or state, use an external pullup or pulldown resistor to pull the signal to the opposite rail.

For the boot and configuration pins (listed in Table 4-1, Boot Terminal Functions), if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup or pulldown resistor be implemented. Although, internal pullup and pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device boot and configuration pins. In addition, applying external pullup or pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup or pulldown resistor:

  • Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.
  • Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which, by definition, have margin to the VIL and VIH levels.
  • Select a pullup or pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup and pulldown resistors on the net.
  • For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).
  • Remember to include tolerances when selecting the resistor value.
  • For pullup resistors, also remember to include tolerances on the DVDD rail.

For most systems, a 1-kΩ resistor can be used to oppose the IPU or IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For most systems, a 20-kΩ resistor can be used to compliment the IPU or IPD on the boot and configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For most systems, a 20-kΩ resistor can also be used as an external pullup or pulldown on the pins that have IPUs or IPDs disabled and require an external pullup or pulldown resistor while still meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (II), and the low-level or high-level input voltages (VIL and VIH), see , Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature.

For the internal pullup and pulldown resistors for all device pins, see the peripheral-specific or system-specific terminal functions tables in Section 4.2.

6.4 Boot Sequence

The boot sequence is a process by which the device's memory is loaded with program and data sections, and by which some of the device's internal registers are programmed with predetermined values. The boot sequence is started automatically after each device-level global reset. For more details on device-level global resets, see Section 8.2. There are several methods by which the memory and register initialization can take place. Each of these methods is referred to as a boot mode. The boot mode to be used is selected at reset. The device is booted through multiple means—primary bootloaders within internal ROM or EMIF4, and secondary user bootloaders from peripherals or external memories. The maximum size of the boot image is 255KB (ROM uses 1KB internally). Boot modes, pin configurations, and register configurations required for booting the device, are described in the following subsections.

The following boot modes are supported:

  • NOR Flash boot (muxed and non-muxed, 8-bit or 16-bit)
  • NAND Flash boot (SLC and MLC with BCH ECC, 8-bit or 16-bit)
  • SPI boot (EEPROM or Flash, SPI mode 3, 24-bit)
  • SD boot (SD cards)
  • EMAC boot (TFTP client)
  • UART boot (X-modem client)
  • PCIe boot (client mode, PCIe 32 and PCIe 64).

The state of the device after boot is determined by sampling the input states of the BTMODE[4:0] pins when device reset (POR or RESET) is deasserted. The sampled values are latched into the CONTROL_STATUS register, which is part of the system configuration (SYSCFG) module.

The BTMODE [4:0] values determine the boot mode order according to Table 6-6. The first boot mode listed for each BTMODE[4:0] configuration is executed as the primary boot mode. If the primary boot mode fails, the second, third, and fourth boot modes are executed, in that order, until a successful boot is completed.

Additional boot configuration pins determine the following system boot settings as shown in Table 4-1:

  • GPMC CS0 Default Bus Width
  • GPMC Wait Enable
  • GPMC Address and Data Multiplexing.

The GPMC CS0 default operation is determined by the CS0BW, CS0WAIT, and CS0MUX[1:0] inputs.

For more detailed information on booting the device, see the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (literature number SPRUGX8).

Table 6-6 Boot Mode Order

BTMODE[4] = 1
MEMORY BOOTING PREFERRED		 BTMODE[4] = 0
PERIPHERAL BOOTING PREFERRED		 BTMODE[3:0]
FIRST SECOND THIRD FOURTH FIRST SECOND THIRD FOURTH
XIP(1) UART EMAC SD RESERVED RESERVED RESERVED RESERVED 0000
XIPWAIT(1) UART EMAC SD UART XIPWAIT(1) SD SPI 0001
NAND NANDI2C SPI UART UART SPI NAND NANDI2C 0010
NAND NANDI2C SD UART UART SPI XIP(1) SD 0011
NAND NANDI2C SPI EMAC EMAC SPI NAND NANDI2C 0100
NANDI2C SD EMAC UART RESERVED RESERVED RESERVED RESERVED 0101
SPI SD UART EMAC RESERVED RESERVED RESERVED RESERVED 0110
SD SPI UART EMAC EMAC SD SPI XIP(1) 0111
SPI SD PCIE_32 RESERVED PCIE_32 RESERVED RESERVED RESERVED 1000
SPI SD PCIE_64 RESERVED PCIE_64 RESERVED RESERVED RESERVED 1001
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 1010
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 1011
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 1100
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 1101
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 1110
GP Fast External Boot EMAC UART PCIE_32 GP Fast External Boot UART EMAC PCIE_64 1111
(1) GPMC CS0 eXecute In Place (XIP) and eXecute In Place with Wait Monitoring (XIPWAIT) boot for NOR. OneNAND, and ROM. For details, see the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (literature number SPRUGX8).

6.4.1 Boot Mode Registers

For details on the boot mode registers, see the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (literature number SPRUGX8).

Table 6-7 Device Boot Registers Summary

HEX ADDRESS ACRONYM REGISTER NAME
0x4814 0040 CONTROL_STATUS Device Status
0x4814 0044 BOOTSTAT Device Boot Status
0x4814 0048 DSPBOOTADDR DSP Boot Address Vector
0x4814 004C - 0x4814 007C - Reserved

6.5 Pin Multiplexing Control

Device-level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCTRL1 - PINCTRL321 registers in the SYSCFG module. The default state for each multiplexed pin is MUXMODE = 0x000.

Pin multiplexing selects which of several peripheral pin functions control the pin's IO buffer output data values.

The input from each pin is routed to all of the peripherals that share the pin, regardless of the MUXMODE setting. For details, see the table below and the MUXED column in the each of the Terminal Functions tables in Section 4.2.

6.5.1 PINCTRLx Register Descriptions

Table 6-8 PINCTRLx Register Definition

Bit Field Value Description
31:5 Reserved Reserved; Read returns 0
4 PULLTYPESEL Pad Pullup or Pulldown Type Selection
0 Pulldown selected
1 Pullup selected
3 PULLDIS Pad Pullup or Pulldown Disable
0 Pullup or Pulldown enabled
1 Pullup or Pulldown disabled
2:0 MUXMODE Pad Functional Signal Mux Select

Table 6-9 PINCTRLx Registers

HEX ADDRESS REGISTER NAME PULLTYPESEL PULLDIS MUXMODE[2:0]
000 001 010 011
0x4814 0800 PINCTRL1 0 0
0x4814 0804 PINCTRL2 0 0
0x4814 0808 PINCTRL3 0 0
0x4814 080C PINCTRL4 0 0
0x4814 0810 PINCTRL5 0 0
0x4814 0814 PINCTRL6 0 0 VOUT[1]_C[3] VIN[1]A_D[9]
0x4814 0818 PINCTRL7 0 0 VOUT[1]_C[4] VIN[1]A_D[10]
0x4814 081C PINCTRL8 0 0 VOUT[1]_C[5] VIN[1]A_D[11]
0x4814 0820 PINCTRL9 0 0 VOUT[1]_C[6] VIN[1]A_D[12]
0x4814 0824 PINCTRL10 0 0 VOUT[1]_C[7] VIN[1]A_D[13]
0x4814 0828 PINCTRL11 0 0 VIN[1]A_D[14]
0x4814 082C PINCTRL12 0 0 VIN[0]A_D[20] VIN[0]B_DE
0x4814 0830 PINCTRL13 0 0 VIN[0]A_D[21] VIN[0]B_FLD
0x4814 0834 PINCTRL14 0 0 VIN[0]A_D[22] VIN[0]B_VSYNC
0x4814 0838 PINCTRL15 0 0 VIN[0]A_D[23] VIN[0]B_HSYNC
0x4814 083C PINCTRL16 0 0 VOUT[1]_Y_YC[6] VIN[1]A_D[4]
0x4814 0840 PINCTRL17 0 0 VOUT[1]_Y_YC[7] VIN[1]A_D[5]
0x4814 0844 PINCTRL18 0 0 VOUT[1]_Y_YC[8] VIN[1]A_D[6]
0x4814 0848 PINCTRL19 0 0 VOUT[1]_Y_YC[9] VIN[1]A_D[7]
0x4814 084C PINCTRL20 0 0 VOUT[1]_C[2] VIN[1]A_D[8]
0x4814 0850 PINCTRL21 0 0 VOUT[1]_HSYNC
(silicon revision 1.x)		 VIN[1]A_D[15]
DAC_VOUT[1]_HSYNC
(silicon revision 2.x)
0x4814 0854 PINCTRL22 0 0 VIN[0]A_D[16] VIN[1]A_HSYNC VOUT[1]_FLD
0x4814 0858 PINCTRL23 0 0 VIN[0]A_D[17] VIN[1]A_VSYNC VOUT[1]_VSYNC
(silicon revision 1.x)
DAC_VOUT[1]_VSYNC
(silicon revision 2.x)
0x4814 085C PINCTRL24 0 0 VIN[0]A_D[18] VIN[1]A_FLD VOUT[1]_C[8]
0x4814 0860 PINCTRL25 0 0 VIN[0]A_D[19] VIN[1]A_DE VOUT[1]_C[9]
0x4814 0864 PINCTRL26 0 0 VOUT[0]_R_CR[0] VOUT[1]_C[8] VOUT[1]_CLK
0x4814 0868 PINCTRL27 0 0 VOUT[0]_B_CB_C[0] VOUT[1]_C[9] VIN[1]B_HSYNC_DE
0x4814 086C PINCTRL28 0 0 VOUT[0]_B_CB_C[1] VOUT[1]_HSYNC
(silicon revision 1.x)		 VOUT[1]_AVID
DAC_VOUT[1]_HSYNC
(silicon revision 2.x)
0x4814 0870 PINCTRL29 0 0 VOUT[0]_G_Y_YC[0] VOUT[1]_VSYNC
(silicon revision 1.x)		 VIN[1]B_VSYNC
DAC_VOUT[1]_VSYNC
(silicon revision 2.x)
0x4814 0874 PINCTRL30 0 0 VOUT[0]_G_Y_YC[1] VOUT[1]_FLD VIN[1]B_FLD
0x4814 0878 PINCTRL31 0 0 VOUT[1]_AVID VIN[1]B_CLK
0x4814 087C PINCTRL32 0 0 VIN[0]A_HSYNC
0x4814 0880 PINCTRL33 0 0 VIN[0]A_VSYNC
0x4814 0884 PINCTRL34 0 0 VIN[0]A_FLD
0x4814 0888 PINCTRL35 0 0 VIN[0]A_DE
0x4814 088C PINCTRL36 0 0 VOUT[0]_HSYNC
0x4814 0890 PINCTRL37 0 0 VOUT[0]_VSYNC
0x4814 0894 PINCTRL38 0 0 VOUT[0]_FLD
(silicon revision 1.x)
DAC_VSYNC_VOUT[0]_FLD
(silicon revision 2.x)
0x4814 0898 PINCTRL39 0 0 VOUT[0]_AVID
(silicon revision 1.x)
DAC_HSYNC_VOUT[0]_AVID
(silicon revision 2.x)
0x4814 089C PINCTRL40 0 0 VOUT[0]_R_CR[1]
0x4814 08A0 PINCTRL41 0 1
0x4814 08A4 PINCTRL42 0 1
0x4814 08A8 PINCTRL43 0 1
0x4814 08AC PINCTRL44 0 1
0x4814 08B0 PINCTRL45 0 1
0x4814 08B4 PINCTRL46 0 1 VOUT[1]_CLK VIN[1]A_CLK
0x4814 08B8 PINCTRL47 0 1 VOUT[1]_Y_YC[2] VIN[1]A_D[0]
0x4814 08BC PINCTRL48 0 1 VOUT[1]_Y_YC[3] VIN[1]A_D[1]
0x4814 08C0 PINCTRL49 0 1 VOUT[1]_Y_YC[4] VIN[1]A_D[2]
0x4814 08C4 PINCTRL50 0 1 VOUT[1]_Y_YC[5] VIN[1]A_D[3]
0x4814 08C8 PINCTRL51 0 0 EMAC[1]_RXCLK
0x4814 08CC PINCTRL52 0 0 EMAC[1]_RXD[0]
0x4814 08D0 PINCTRL53 0 0 EMAC[1]_RXD[1]
0x4814 08D4 PINCTRL54 0 0 EMAC[1]_RXD[2]
0x4814 08D8 PINCTRL55 0 0 EMAC[1]_RXD[3]
0x4814 08DC PINCTRL56 0 0 EMAC[1]_RXD[4]
0x4814 08E0 PINCTRL57 0 0 EMAC[1]_RXD[5]
0x4814 08E4 PINCTRL58 0 0 EMAC[1]_RXD[6]
0x4814 08E8 PINCTRL59 0 0 EMAC[1]_RXD[7]
0x4814 08EC PINCTRL60 0 0 EMAC[1]_RXDV
0x4814 08F0 PINCTRL61 0 1 EMAC[1]_GMTCLK
0x4814 08F4 PINCTRL62 0 1 EMAC[1]_TXD[0]
0x4814 08F8 PINCTRL63 0 1 EMAC[1]_TXD[1]
0x4814 08FC PINCTRL64 0 1 EMAC[1]_TXD[2]
0x4814 0900 PINCTRL65 0 1 EMAC[1]_TXD[3]
0x4814 0904 PINCTRL66 0 1 EMAC[1]_TXD[4]
0x4814 0908 PINCTRL67 0 1 EMAC[1]_TXD[5]
0x4814 090C PINCTRL68 0 1 EMAC[1]_TXD[6]
0x4814 0910 PINCTRL69 0 1 EMAC[1]_TXD[7]
0x4814 0914 PINCTRL70 0 1 EMAC[1]_TXEN
0x4814 0918 PINCTRL71 0 1 EMAC[1]_TXCLK
0x4814 091C PINCTRL72 0 1 EMAC[1]_COL
0x4814 0920 PINCTRL73 0 0 EMAC[1]_CRS
0x4814 0924 PINCTRL74 0 1 EMAC[1]_RXER
0x4814 0928 PINCTRL75 0 0
0x4814 092C PINCTRL76 0 0
0x4814 0930 PINCTRL77 0 0
0x4814 0934 PINCTRL78 0 0
0x4814 0938 PINCTRL79 0 0
0x4814 093C PINCTRL80 0 1
0x4814 0940 PINCTRL81 0 1
0x4814 0944 PINCTRL82 0 1
0x4814 0948 PINCTRL83 0 0 VIN[0]A_CLK
0x4814 094C PINCTRL84 0 0 VIN[0]B_CLK
0x4814 0950 PINCTRL85 0 0 VIN[0]A_D[0]
0x4814 0954 PINCTRL86 0 0 VIN[0]A_D[1]
0x4814 0958 PINCTRL87 0 0 VIN[0]A_D[2]
0x4814 095C PINCTRL88 0 0 VIN[0]A_D[3]
0x4814 0960 PINCTRL89 0 0 VIN[0]A_D[4]
0x4814 0964 PINCTRL90 0 0 VIN[0]A_D[5]
0x4814 0968 PINCTRL91 0 0 VIN[0]A_D[6]
0x4814 096C PINCTRL92 0 0 VIN[0]A_D[7]
0x4814 0970 PINCTRL93 0 0 VIN[0]A_D[8]
0x4814 0974 PINCTRL94 0 0 VIN[0]A_D[9]
0x4814 0978 PINCTRL95 0 0 VIN[0]A_D[10]
0x4814 097C PINCTRL96 0 0 VIN[0]A_D[11]
0x4814 0980 PINCTRL97 0 0 VIN[0]A_D[12]
0x4814 0984 PINCTRL98 0 0 VIN[0]A_D[13]
0x4814 0988 PINCTRL99 0 0 VIN[0]A_D[14]
0x4814 098C PINCTRL100 0 0 VIN[0]A_D[15]
0x4814 0990 PINCTRL101 0 1 VOUT[0]_CLK
0x4814 0994 PINCTRL102 0 1 VOUT[0]_G_Y_YC[2]
0x4814 0998 PINCTRL103 0 1 VOUT[0]_G_Y_YC[3]
0x4814 099C PINCTRL104 0 1 VOUT[0]_G_Y_YC[4]
0x4814 09A0 PINCTRL105 0 1 VOUT[0]_G_Y_YC[5]
0x4814 09A4 PINCTRL106 0 1 VOUT[0]_G_Y_YC[6]
0x4814 09A8 PINCTRL107 0 1 VOUT[0]_G_Y_YC[7]
0x4814 09AC PINCTRL108 0 1 VOUT[0]_G_Y_YC[8]
0x4814 09B0 PINCTRL109 0 1 VOUT[0]_G_Y_YC[9]
0x4814 09B4 PINCTRL110 0 1 VOUT[0]_B_CB_C[2]
0x4814 09B8 PINCTRL111 0 1 VOUT[0]_B_CB_C[3]
0x4814 09BC PINCTRL112 0 1 VOUT[0]_B_CB_C[4]
0x4814 09C0 PINCTRL113 0 1 VOUT[0]_B_CB_C[5]
0x4814 09C4 PINCTRL114 0 1 VOUT[0]_B_CB_C[6]
0x4814 09C8 PINCTRL115 0 1 VOUT[0]_B_CB_C[7]
0x4814 09CC PINCTRL116 0 1 VOUT[0]_B_CB_C[8]
0x4814 09D0 PINCTRL117 0 1 VOUT[0]_B_CB_C[9]
0x4814 09D4 PINCTRL118 0 1 VOUT[0]_R_CR[2] VOUT[0]_HSYNC VOUT[1]_Y_YC[2]
0x4814 09D8 PINCTRL119 0 1 VOUT[0]_R_CR[3] VOUT[0]_VSYNC VOUT[1]_Y_YC[3]
0x4814 09DC PINCTRL120 0 1 VOUT[0]_R_CR[4] VOUT[0]_FLD VOUT[1]_Y_YC[4]
0x4814 09E0 PINCTRL121 0 1 VOUT[0]_R_CR[5] VOUT[0]_AVID VOUT[1]_Y_YC[5]
0x4814 09E4 PINCTRL122 0 1 VOUT[0]_R_CR[6] VOUT[0]_G_Y_YC[0] VOUT[1]_Y_YC[6]
0x4814 09E8 PINCTRL123 0 1 VOUT[0]_R_CR[7] VOUT[0]_G_Y_YC[1] VOUT[1]_Y_YC[7]
0x4814 09EC PINCTRL124 0 1 VOUT[0]_R_CR[8] VOUT[0]_B_CB_C[0] VOUT[1]_Y_YC[8]
0x4814 09F0 PINCTRL125 0 1 VOUT[0]_R_CR[9] VOUT[0]_B_CB_C[1] VOUT[1]_Y_YC[9]
0x4814 09F4 PINCTRL126 0 0 MCA[0]_ACLKR
0x4814 09F8 PINCTRL127 0 0 MCA[0]_AHCLKR
0x4814 09FC PINCTRL128 0 0 MCA[0]_AFSR
0x4814 0A00 PINCTRL129 0 0 MCA[0]_ACLKX
0x4814 0A04 PINCTRL130 0 0 MCA[0]_ACLKHX
0x4814 0A08 PINCTRL131 0 0 MCA[0]_AFSX
0x4814 0A0C PINCTRL132 0 0 MCA[0]_AMUTE
0x4814 0A10 PINCTRL133 0 0 MCA[0]_AXR[0]
0x4814 0A14 PINCTRL134 0 0 MCA[0]_AXR[1]
0x4814 0A18 PINCTRL135 0 0 MCA[0]_AXR[2] MCB_FSX
0x4814 0A1C PINCTRL136 0 0 MCA[0]_AXR[3] MCB_FSR
0x4814 0A20 PINCTRL137 0 0 MCA[0]_AXR[4] MCB_DX
0x4814 0A24 PINCTRL138 0 0 MCA[0]_AXR[5] MCB_DR
0x4814 0A28 PINCTRL139 0 0 MCA[1]_ACLKR
0x4814 0A2C PINCTRL140 0 0 MCA[1]_AHCLKR
0x4814 0A30 PINCTRL141 0 0 MCA[1]_AFSR
0x4814 0A34 PINCTRL142 0 0 MCA[1]_ACLKX
0x4814 0A38 PINCTRL143 0 0 MCA[1]_ACLKHX
0x4814 0A3C PINCTRL144 0 0 MCA[1]_AFSX
0x4814 0A40 PINCTRL145 0 0 MCA[1]_AMUTE
0x4814 0A44 PINCTRL146 0 0 MCA[1]_AXR[0]
0x4814 0A48 PINCTRL147 0 0 MCA[1]_AXR[1]
0x4814 0A4C PINCTRL148 0 0 MCA[2]_ACLKR MCB_CLKR MCB_DR
0x4814 0A50 PINCTRL149 0 0 MCA[2]_AHCLKR MCB_CLKS
0x4814 0A54 PINCTRL150 0 0 MCA[2]_AFSR MCB_CLKX MCB_FSR
0x4814 0A58 PINCTRL151 0 0 MCA[2]_ACLKX MCB_CLKX
0x4814 0A5C PINCTRL152 0 0 MCA[2]_ACLKHX MCB_CLKR
0x4814 0A60 PINCTRL153 0 0 MCA[2]_AFSX MCB_CLKS MCB_FSX
0x4814 0A64 PINCTRL154 0 0 MCA[2]_AMUTE
0x4814 0A68 PINCTRL155 0 0 MCA[2]_AXR[0]
0x4814 0A6C PINCTRL156 0 0 MCA[2]_AXR[1] MCB_DX
0x4814 0A70 PINCTRL157 0 1 SD_POW GPMC_A[14] GP1[0]
0x4814 0A74 PINCTRL158 0 1 SD_CLK GPMC_A[13] GP1[1]
0x4814 0A78 PINCTRL159 0 1 SD_CMD GPMC_A[21] GP1[2]
0x4814 0A7C PINCTRL160 0 0 SD_DAT[0] GPMC_A[20] GP1[3]
0x4814 0A80 PINCTRL161 0 0 SD_DAT[1]_SDIRQ GPMC_A[19] GP1[4]
0x4814 0A84 PINCTRL162 0 0 SD_DAT[2]_SDRW GPMC_A[18] GP1[5]
0x4814 0A88 PINCTRL163 0 0 SD_DAT[3] GPMC_A[17] GP1[6]
0x4814 0A8C PINCTRL164 0 0 SD_SDCD GPMC_A[16] GP1[7]
0x4814 0A90 PINCTRL165 0 0 SD_SDWP GPMC_A[15] GP1[8]
0x4814 0A94 PINCTRL166 0 0 SPI_SCLK
0x4814 0A98 PINCTRL167 1 0 SPI_SCS[0]
0x4814 0A9C PINCTRL168 1 0 SPI_SCS[1] GPMC_A[23]
0x4814 0AA0 PINCTRL169 1 0 SPI_SCS[2] GPMC_A[22]
0x4814 0AA4 PINCTRL170 1 0 SPI_SCS[3] GPMC_A[21] GP1[22]
0x4814 0AA8 PINCTRL171 0 0 SPI_D[0]
0x4814 0AAC PINCTRL172 0 0 SPI_D[1]
0x4814 0AB0 PINCTRL173 0 0 UART0_RXD
0x4814 0AB4 PINCTRL174 0 1 UART0_TXD
0x4814 0AB8 PINCTRL175 1 1 UART0_RTS GP1[27]
0x4814 0ABC PINCTRL176 1 0 UART0_CTS GP1[28]
0x4814 0AC0 PINCTRL177 1 1 UART0_DTR GPMC_A[20] GPMC_A[12] GP1[16]
0x4814 0AC4 PINCTRL178 1 0 UART0_DSR GPMC_A[19] GPMC_A[24] GP1[17]
0x4814 0AC8 PINCTRL179 1 0 UART0_DCD GPMC_A[18] GPMC_A[23] GP1[18]
0x4814 0ACC PINCTRL180 1 0 UART0_RIN GPMC_A[17] GPMC_A[22] GP1[19]
0x4814 0AD0 PINCTRL181 0 0 UART1_RXD GPMC_A[26] GPMC_A[20]
0x4814 0AD4 PINCTRL182 0 1 UART1_TXD GPMC_A[25] GPMC_A[19]
0x4814 0AD8 PINCTRL183 1 1 UART1_RTS GPMC_A[14] GPMC_A[18] GP1[25]
0x4814 0ADC PINCTRL184 1 0 UART1_CTS GPMC_A[13] GPMC_A[17] GP1[26]
0x4814 0AE0 PINCTRL185 0 0 UART2_RXD
0x4814 0AE4 PINCTRL186 0 0 UART2_TXD
0x4814 0AE8 PINCTRL187 1 1 UART2_RTS GPMC_A[15] GPMC_A[26] GP1[23]
0x4814 0AEC PINCTRL188 1 0 UART2_CTS GPMC_A[16] GPMC_A[25] GP1[24]
0x4814 0AF0 PINCTRL189 0 0 GPMC_A[27] GP1[9]
0x4814 0AF4 PINCTRL190 0 1 GPMC_A[22] GP1[10]
0x4814 0AF8 PINCTRL191 0 1 GPMC_A[26] GP1[11]
0x4814 0AFC PINCTRL192 0 0 GPMC_A[25] GP1[12]
0x4814 0B00 PINCTRL193 0 1 GP1[13]
0x4814 0B04 PINCTRL194 0 1 GPMC_A[23] GP1[14]
0x4814 0B08 PINCTRL195 0 1 GPMC_A[24] GP1[15]
0x4814 0B0C PINCTRL196 0 0 GPMC_A[16] GP0[21]
0x4814 0B10 PINCTRL197 0 1 GPMC_A[15] GP0[22]
0x4814 0B14 PINCTRL198 0 1 GPMC_A[14] GP0[23]
0x4814 0B18 PINCTRL199 0 0 GPMC_A[13] GP0[24]
0x4814 0B1C PINCTRL200 0 1 GP0[25]
0x4814 0B20 PINCTRL201 0 1 GPMC_A[21] GP0[26]
0x4814 0B24 PINCTRL202 0 1 GPMC_A[12] GP0[27]
0x4814 0B28 PINCTRL203 0 0 TIM4_OUT GP0[28]
0x4814 0B2C PINCTRL204 0 0 TIM5_OUT GP0[29]
0x4814 0B30 PINCTRL205 0 0 TIM6_OUT GPMC_A[24] GP0[30]
0x4814 0B34 PINCTRL206 0 0 TIM7_OUT GPMC_A[12] GP0[31]
0x4814 0B38 PINCTRL207 1 0 GPMC_CS[0]
0x4814 0B3C PINCTRL208 1 0 GPMC_CS[1]
0x4814 0B40 PINCTRL209 1 0 GPMC_CS[2]
0x4814 0B44 PINCTRL210 1 0 GPMC_CS[3]
0x4814 0B48 PINCTRL211 1 0 GPMC_CS[4] GP1[21]
0x4814 0B4C PINCTRL212 1 0 GPMC_CS[5] GPMC_A[12]
0x4814 0B50 PINCTRL213 1 0 GPMC_WE
0x4814 0B54 PINCTRL214 1 1 GPMC_OE_RE
0x4814 0B58 PINCTRL215 0 1 GPMC_BE0_CLE
0x4814 0B5C PINCTRL216 0 1 GPMC_BE1
0x4814 0B60 PINCTRL217 0 1 GPMC_ADV_ALE
0x4814 0B64 PINCTRL218 0 1 GPMC_DIR GP1[20]
0x4814 0B68 PINCTRL219 0 0 GPMC_WP
0x4814 0B6C PINCTRL220 0 0 GPMC_WAIT
0x4814 0B70 PINCTRL221 0 1 GPMC_A[0] GP0[8]
0x4814 0B74 PINCTRL222 0 1 GPMC_A[1] GP0[9]
0x4814 0B78 PINCTRL223 0 1 GPMC_A[2] GP0[10]
0x4814 0B7C PINCTRL224 0 1 GPMC_A[3] GP0[11]
0x4814 0B80 PINCTRL225 0 1 GPMC_A[4] GP0[12]
0x4814 0B84 PINCTRL226 0 1 GPMC_A[5] GP0[13]
0x4814 0B88 PINCTRL227 0 1 GPMC_A[6] GP0[14]
0x4814 0B8C PINCTRL228 0 1 GPMC_A[7] GP0[15]
0x4814 0B90 PINCTRL229 0 1 GPMC_A[8] GP0[16]
0x4814 0B94 PINCTRL230 0 1 GPMC_A[9] GP0[17]
0x4814 0B98 PINCTRL231 0 1 GPMC_A[10] GP0[18]
0x4814 0B9C PINCTRL232 0 1 GPMC_A[11] GP0[19]
0x4814 0BA0 PINCTRL233 0 1 GPMC_A[27] GP0[20]
0x4814 0BA4 PINCTRL234 0 0 GPMC_D[0]
0x4814 0BA8 PINCTRL235 0 0 GPMC_D[1]
0x4814 0BAC PINCTRL236 0 0 GPMC_D[2]
0x4814 0BB0 PINCTRL237 0 0 GPMC_D[3]
0x4814 0BB4 PINCTRL238 0 0 GPMC_D[4]
0x4814 0BB8 PINCTRL239 0 0 GPMC_D[5]
0x4814 0BBC PINCTRL240 0 0 GPMC_D[6]
0x4814 0BC0 PINCTRL241 0 0 GPMC_D[7]
0x4814 0BC4 PINCTRL242 0 0 GPMC_D[8]
0x4814 0BC8 PINCTRL243 0 0 GPMC_D[9]
0x4814 0BCC PINCTRL244 0 0 GPMC_D[10]
0x4814 0BD0 PINCTRL245 0 0 GPMC_D[11]
0x4814 0BD4 PINCTRL246 0 0 GPMC_D[12]
0x4814 0BD8 PINCTRL247 0 0 GPMC_D[13]
0x4814 0BDC PINCTRL248 0 0 GPMC_D[14]
0x4814 0BE0 PINCTRL249 0 0 GPMC_D[15]
0x4814 0BE4 PINCTRL250 0 1 GPMC_CLK GP1[29]
0x4814 0BE8 PINCTRL251 0 0 EMAC[0]_COL
0x4814 0BEC PINCTRL252 0 0 EMAC[0]_CRS
0x4814 0BF0 PINCTRL253 0 1 EMAC[0]_GMTCLK
0x4814 0BF4 PINCTRL254 1 0 EMAC[0]_RXCLK
0x4814 0BF8 PINCTRL255 1 0 EMAC[0]_RXD[0]
0x4814 0BFC PINCTRL256 1 0 EMAC[0]_RXD[1]
0x4814 0C00 PINCTRL257 1 0 EMAC[0]_RXD[2]
0x4814 0C04 PINCTRL258 1 0 EMAC[0]_RXD[3]
0x4814 0C08 PINCTRL259 1 0 EMAC[0]_RXD[4]
0x4814 0C0C PINCTRL260 1 0 EMAC[0]_RXD[5]
0x4814 0C10 PINCTRL261 1 0 EMAC[0]_RXD[6]
0x4814 0C14 PINCTRL262 1 0 EMAC[0]_RXD[7]
0x4814 0C18 PINCTRL263 1 0 EMAC[0]_RXDV
0x4814 0C1C PINCTRL264 1 0 EMAC[0]_RXER
0x4814 0C20 PINCTRL265 0 1 EMAC[0]_TXCLK
0x4814 0C24 PINCTRL266 0 1 EMAC[0]_TXD[0]
0x4814 0C28 PINCTRL267 0 1 EMAC[0]_TXD[1]
0x4814 0C2C PINCTRL268 0 1 EMAC[0]_TXD[2]
0x4814 0C30 PINCTRL269 0 1 EMAC[0]_TXD[3]
0x4814 0C34 PINCTRL270 0 1 EMAC[0]_TXD[4]
0x4814 0C38 PINCTRL271 0 1 EMAC[0]_TXD[5]
0x4814 0C3C PINCTRL272 0 1 EMAC[0]_TXD[6]
0x4814 0C40 PINCTRL273 0 1 EMAC[0]_TXD[7]
0x4814 0C44 PINCTRL274 0 1 EMAC[0]_TXEN
0x4814 0C48 PINCTRL275 1 0 MDIO_MCLK
0x4814 0C4C PINCTRL276 1 0 MDIO_MDIO
0x4814 0C50 PINCTRL277 1 0
0x4814 0C54 PINCTRL278 1 0
0x4814 0C58 PINCTRL279 0 1
0x4814 0C5C PINCTRL280 0 1
0x4814 0C60 PINCTRL281 0 1
0x4814 0C64 PINCTRL282 0 1
0x4814 0C68 PINCTRL283 0 0
0x4814 0C6C PINCTRL284 0 0
0x4814 0C70 PINCTRL285 0 0
0x4814 0C74 PINCTRL286 0 0
0x4814 0C78 PINCTRL287 1 1 I2C[0]_SCL
0x4814 0C7C PINCTRL288 1 1 I2C[0]_SDA
0x4814 0C80 PINCTRL289 1 1 I2C[1]_SCL
0x4814 0C84 PINCTRL290 1 1 I2C[1]_SDA
0x4814 0C88 PINCTRL291 0 0 GP0[0]
0x4814 0C8C PINCTRL292 0 0 GP0[1]
0x4814 0C90 PINCTRL293 0 0 GP0[2]
0x4814 0C94 PINCTRL294 0 0 GP0[3] TCLKIN
0x4814 0C98 PINCTRL295 0 0 GP0[4]
0x4814 0C9C PINCTRL296 0 0 GP0[5] MCA[2]_AMUTEIN GPMC_A[24]
0x4814 0CA0 PINCTRL297 0 0 GP0[6] MCA[1]_AMUTEIN GPMC_A[23]
0x4814 0CA4 PINCTRL298 0 0 GP0[7] MCA[0]_AMUTEIN
0x4814 0CA8 PINCTRL299 0 0 GP1[30] SATA_ACT0_LED
(silicon revision 1.x)
SATA_ACT1_LED
(silicon revision 2.x)
0x4814 0CAC PINCTRL300 0 0 GP1[31] SATA_ACT1_LED
(silicon revision 1.x)
SATA_ACT0_LED
(silicon revision 2.x)
0x4814 0CB0 PINCTRL301 0 1 HDMI_SCL
0x4814 0CB4 PINCTRL302 0 1 HDMI_SDA
0x4814 0CB8 PINCTRL303 1 0 HDMI_CEC
0x4814 0CBC PINCTRL304 0 0 HDMI_HPDET
0x4814 0CC0 PINCTRL305 1 0 TCLK
0x4814 0CC4 PINCTRL306 0 1 RTCK
0x4814 0CC8 PINCTRL307 1 0 TDI
0x4814 0CCC PINCTRL308 0 1 TDO
0x4814 0CD0 PINCTRL309 1 0 TMS
0x4814 0CD4 PINCTRL310 0 0 TRST
0x4814 0CD8 PINCTRL311 1 0 EMU0
0x4814 0CDC PINCTRL312 1 0 EMU1
0x4814 0CE0 PINCTRL313 1 0 EMU2
0x4814 0CE4 PINCTRL314 1 0 EMU3
0x4814 0CE8 PINCTRL315 1 0 EMU4
0x4814 0CEC PINCTRL316 1 0 RESET
0x4814 0CF0 PINCTRL317 1 0 NMI
0x4814 0CF4 PINCTRL318 1 0 RSTOUT
0x4814 0CF8 PINCTRL319 1 0 WD_OUT
0x4814 0CFC PINCTRL320 0 1 CLKOUT
0x4814 0D00 PINCTRL321 0 0 CLKIN32
0x4814 0D04 PINCTRL322 0 0 USB0_DRVVBUS
0x4814 0D08 PINCTRL323 0 0 USB1_DRVVBUS
0x4814 0D0C - 0x4814 0FFF Reserved

6.6 How to Handle Unused Pins

When device signal pins are unused in the system, they can be left unconnected unless otherwise instructed in the Terminal Functions tables. For unused input pins, the internal pull resistor should be enabled, or an external pull resistor should be used, to prevent floating inputs. All supply pins must always be connected to the correct voltage, even when their associated signal pins are unused, as instructed in the Terminal Functions tables in Section 4.2.