SPRS614F March   2011  – March 2015 TMS320DM8165 , TMS320DM8167 , TMS320DM8168

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 ARM Subsystem
      1. 3.2.1 ARM Cortex-A8 RISC Processor
      2. 3.2.2 Embedded Trace Module (ETM)
      3. 3.2.3 ARM Cortex-A8 Interrupt Controller (AINTC)
      4. 3.2.4 System Interconnect
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 System Memory Management Unit (System MMU)
        1. 3.3.2.1 System MMU Registers
    4. 3.4 Media Controller
    5. 3.5 High-Definition Video Image Coprocessor 2 (HDVICP2)
    6. 3.6 Inter-Processor Communication
      1. 3.6.1 Mailbox Module
        1. 3.6.1.1 Mailbox Registers
      2. 3.6.2 Spinlock Module
        1. 3.6.2.1 Spinlock Registers
    7. 3.7 Power, Reset and Clock Management (PRCM) Module
    8. 3.8 SGX530 (DM8168 only)
    9. 3.9 Memory Map Summary
      1. 3.9.1 L3 Memory Map
      2. 3.9.2 L4 Memory Map
        1. 3.9.2.1 L4 Standard Peripheral
        2. 3.9.2.2 L4 High-Speed Peripheral
      3. 3.9.3 TILER Extended Addressing Map
      4. 3.9.4 Cortex™-A8 Memory Map
      5. 3.9.5 C674x Memory Map
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Assignments
      1. 4.1.1 Pin Map (Bottom View)
    2. 4.2 Terminal Functions
      1. 4.2.1  Boot Configuration
      2. 4.2.2  DDR2 and DDR3 Memory Controller Signals
      3. 4.2.3  Ethernet Media Access Controller (EMAC) Signals
      4. 4.2.4  General-Purpose Input/Output (GPIO) Signals
      5. 4.2.5  General-Purpose Memory Controller (GPMC) Signals
      6. 4.2.6  High-Definition Multimedia Interface (HDMI) Signals
      7. 4.2.7  Inter-Integrated Circuit (I2C) Signals
      8. 4.2.8  Multichannel Audio Serial Port Signals
      9. 4.2.9  Multichannel Buffered Serial Port Signals
      10. 4.2.10 Oscillator/Phase-Locked Loop (PLL) Signals
      11. 4.2.11 Peripheral Component Interconnect Express (PCIe) Signals
      12. 4.2.12 Reset, Interrupts, and JTAG Interface Signals
      13. 4.2.13 Secure Digital/Secure Digital Input Output (SD/SDIO) Signals
      14. 4.2.14 Serial ATA Signals
      15. 4.2.15 Serial Peripheral Digital Interconnect Format (SPI) Signals
      16. 4.2.16 Timer Signals
      17. 4.2.17 Universal Asynchronous Receiver/Transmitter (UART) Signals
      18. 4.2.18 Universal Serial Bus (USB) Signals
      19. 4.2.19 Video Input Signals
      20. 4.2.20 Digital Video Output Signals
      21. 4.2.21 Analog Video Output Signals
      22. 4.2.22 Reserved Pins
      23. 4.2.23 Supply Voltages
      24. 4.2.24 Ground Pins (VSS)
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (Unless Otherwise Noted)
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Resistance Characteristics
  6. 6 Device Configurations
    1. 6.1 Control Module
    2. 6.2 Revision Identification
    3. 6.3 Debugging Considerations
      1. 6.3.1 Pullup and Pulldown Resistors
    4. 6.4 Boot Sequence
      1. 6.4.1 Boot Mode Registers
    5. 6.5 Pin Multiplexing Control
      1. 6.5.1 PINCTRLx Register Descriptions
    6. 6.6 How to Handle Unused Pins
  7. 7 System Interconnect
    1. 7.1 L3 Interconnect
    2. 7.2 L4 Interconnect
  8. 8 Power, Reset, Clocking, and Interrupts
    1. 8.1 Power Supplies
      1. 8.1.1 Voltage and Power Domains
      2. 8.1.2 Power Domains
      3. 8.1.3 1-V AVS and 1-V Constant Power Domains
      4. 8.1.4 SmartReflex™
      5. 8.1.5 Memory Power Management
      6. 8.1.6 IO Power-Down Modes
      7. 8.1.7 Supply Sequencing
      8. 8.1.8 Power-Supply Decoupling
    2. 8.2 Reset
      1. 8.2.1  System-Level Reset Sources
      2. 8.2.2  Power-On Reset (POR pin)
      3. 8.2.3  External Warm Reset (RESET pin)
      4. 8.2.4  Emulation Warm Reset
      5. 8.2.5  Watchdog Reset
      6. 8.2.6  Software Global Cold Reset
      7. 8.2.7  Software Global Warm Reset
      8. 8.2.8  Test Reset (TRST pin)
      9. 8.2.9  Local Reset
      10. 8.2.10 Reset Priority
      11. 8.2.11 Reset Status Register
      12. 8.2.12 PCIe Reset Isolation
      13. 8.2.13 RSTOUT
      14. 8.2.14 Effect of Reset on Emulation and Trace
      15. 8.2.15 Reset During Power Domain Switching
      16. 8.2.16 Pin Behaviors at Reset
      17. 8.2.17 Reset Electrical Data and Timing
    3. 8.3 Clocking
      1. 8.3.1 Device Clock Inputs
        1. 8.3.1.1 Using the Internal Oscillators
      2. 8.3.2 SERDES_CLKN and SERDES_CLKP Input Clock
      3. 8.3.3 CLKIN32 Input Clock
      4. 8.3.4 PLLs
        1. 8.3.4.1 PLL Programming Limits
        2. 8.3.4.2 PLL Power Supply Filtering
        3. 8.3.4.3 PLL Locking Sequence
        4. 8.3.4.4 PLL Registers
      5. 8.3.5 SYSCLKs
      6. 8.3.6 Module Clocks
      7. 8.3.7 Output Clock Select Logic
    4. 8.4 Interrupts
      1. 8.4.1 Interrupt Summary List
      2. 8.4.2 Cortex™-A8 Interrupts
      3. 8.4.3 C674x Interrupts
  9. 9 Peripheral Information and Timings
    1. 9.1  Parameter Information
      1. 9.1.1 1.8-V and 3.3-V Signal Transition Levels
      2. 9.1.2 3.3-V Signal Transition Rates
      3. 9.1.3 Timing Parameters and Board Routing Analysis
    2. 9.2  Recommended Clock and Control Signal Transition Behavior
    3. 9.3  DDR2 and DDR3 Memory Controller
      1. 9.3.1 DDR2 Routing Specifications
        1. 9.3.1.1 Board Designs
        2. 9.3.1.2 DDR2 Interface
          1. 9.3.1.2.1  DDR2 Interface Schematic
          2. 9.3.1.2.2  Compatible JEDEC DDR2 Devices
          3. 9.3.1.2.3  PCB Stackup
          4. 9.3.1.2.4  Placement
          5. 9.3.1.2.5  DDR2 Keepout Region
          6. 9.3.1.2.6  Bulk Bypass Capacitors
          7. 9.3.1.2.7  High-Speed Bypass Capacitors
          8. 9.3.1.2.8  Net Classes
          9. 9.3.1.2.9  DDR2 Signal Termination
          10. 9.3.1.2.10 VREFSSTL_DDR Routing
        3. 9.3.1.3 DDR2 CK and ADDR_CTRL Routing
      2. 9.3.2 DDR3 Routing Specifications
        1. 9.3.2.1  Board Designs
          1. 9.3.2.1.1 DDR3 versus DDR2
        2. 9.3.2.2  DDR3 Device Combinations
          1. 9.3.2.2.1 DDR3 EMIFs
        3. 9.3.2.3  DDR3 Interface Schematic
          1. 9.3.2.3.1 32-Bit DDR3 Interface
          2. 9.3.2.3.2 16-Bit DDR3 Interface
        4. 9.3.2.4  Compatible JEDEC DDR3 Devices
        5. 9.3.2.5  PCB Stackup
        6. 9.3.2.6  Placement
        7. 9.3.2.7  DDR3 Keepout Region
        8. 9.3.2.8  Bulk Bypass Capacitors
        9. 9.3.2.9  High-Speed Bypass Capacitors
          1. 9.3.2.9.1 Return Current Bypass Capacitors
        10. 9.3.2.10 Net Classes
        11. 9.3.2.11 DDR3 Signal Termination
        12. 9.3.2.12 VREFSSTL_DDR Routing
        13. 9.3.2.13 VTT
        14. 9.3.2.14 CK and ADDR_CTRL Topologies and Routing Definition
          1. 9.3.2.14.1 Four DDR3 Devices
            1. 9.3.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 9.3.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 9.3.2.14.2 Two DDR3 Devices
            1. 9.3.2.14.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 9.3.2.14.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 9.3.2.14.3 One DDR3 Device
            1. 9.3.2.14.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 9.3.2.14.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
        15. 9.3.2.15 Data Topologies and Routing Definition
          1. 9.3.2.15.1 DQS, DQ and DM Topologies, Any Number of Allowed DDR3 Devices
          2. 9.3.2.15.2 DQS, DQ and DM Routing, Any Number of Allowed DDR3 Devices
        16. 9.3.2.16 Routing Specification
          1. 9.3.2.16.1 CK and ADDR_CTRL Routing Specification
          2. 9.3.2.16.2 DQS and DQ Routing Specification
      3. 9.3.3 DDR2 and DDR3 Memory Controller Register Descriptions
      4. 9.3.4 DDR2 and DDR3 PHY Register Descriptions
      5. 9.3.5 DDR2 and DDR3 Memory Controller Electrical Data and Timing
    4. 9.4  Emulation Features and Capability
      1. 9.4.1 Advanced Event Triggering (AET)
      2. 9.4.2 Trace
      3. 9.4.3 IEEE 1149.1 JTAG
        1. 9.4.3.1 JTAG ID (JTAGID) Register Description
        2. 9.4.3.2 JTAG Electrical Data and Timing
      4. 9.4.4 IEEE 1149.7 cJTAG
    5. 9.5  Enhanced Direct Memory Access (EDMA) Controller
      1. 9.5.1 EDMA Channel Synchronization Events
      2. 9.5.2 EDMA Peripheral Register Descriptions
    6. 9.6  Ethernet Media Access Controller (EMAC)
      1. 9.6.1 EMAC Peripheral Register Descriptions
      2. 9.6.2 EMAC Electrical Data and Timing
      3. 9.6.3 Management Data Input and Output (MDIO)
        1. 9.6.3.1 MDIO Peripheral Register Descriptions
        2. 9.6.3.2 MDIO Electrical Data and Timing
    7. 9.7  General-Purpose Input and Output (GPIO)
      1. 9.7.1 GPIO Peripheral Register Descriptions
      2. 9.7.2 GPIO Electrical Data and Timing
    8. 9.8  General-Purpose Memory Controller (GPMC) and Error Locator Module (ELM)
      1. 9.8.1 GPMC and ELM Peripheral Register Descriptions
      2. 9.8.2 GPMC Electrical Data and Timing
        1. 9.8.2.1 GPMC and NOR Flash Interface Synchronous Mode Timing
        2. 9.8.2.2 GPMC and NOR Flash Interface Asynchronous Mode Timing
        3. 9.8.2.3 GPMC and NAND Flash Interface Asynchronous Mode Timing
    9. 9.9  High-Definition Multimedia Interface (HDMI)
      1. 9.9.1 HDMI Interface Design Specifications
        1. 9.9.1.1 HDMI Interface Schematic
        2. 9.9.1.2 TMDS Routing
        3. 9.9.1.3 DDC Signals
        4. 9.9.1.4 HDMI ESD Protection Device (Required)
        5. 9.9.1.5 PCB Stackup Specifications
        6. 9.9.1.6 Grounding
      2. 9.9.2 HDMI Peripheral Register Descriptions
    10. 9.10 High-Definition Video Processing Subsystem (HDVPSS)
      1. 9.10.1 HDVPSS Electrical Data and Timing
      2. 9.10.2 Video DAC Guidelines and Electrical Data and Timing
    11. 9.11 Inter-Integrated Circuit (I2C)
      1. 9.11.1 I2C Peripheral Register Descriptions
      2. 9.11.2 I2C Electrical Data and Timing
    12. 9.12 Multichannel Audio Serial Port (McASP)
      1. 9.12.1 McASP Device-Specific Information
      2. 9.12.2 McASP0, McASP1, and McASP2 Peripheral Register Descriptions
      3. 9.12.3 McASP Electrical Data and Timing
    13. 9.13 Multichannel Buffered Serial Port (McBSP)
      1. 9.13.1 McBSP Peripheral Registers
      2. 9.13.2 McBSP Electrical Data and Timing
    14. 9.14 Peripheral Component Interconnect Express (PCIe)
      1. 9.14.1 PCIe Design and Layout Specifications
        1. 9.14.1.1 Clock Source
        2. 9.14.1.2 PCIe Connections and Interface Compliance
          1. 9.14.1.2.1 Coupling Capacitors
          2. 9.14.1.2.2 Polarity Inversion
          3. 9.14.1.2.3 Lane Reversal
        3. 9.14.1.3 Non-Standard PCIe Connections
          1. 9.14.1.3.1 PCB Stackup Specifications
          2. 9.14.1.3.2 Routing Specifications
      2. 9.14.2 PCIe Peripheral Register Descriptions
      3. 9.14.3 PCIe Electrical Data and Timing
    15. 9.15 Real-Time Clock (RTC)
      1. 9.15.1 RTC Register Descriptions
    16. 9.16 Secure Digital and Secure Digital Input Output (SD and SDIO)
      1. 9.16.1 SD and SDIO Peripheral Register Descriptions
      2. 9.16.2 SD and SDIO Electrical Data and Timing
        1. 9.16.2.1 SD Identification and Standard SD Mode
        2. 9.16.2.2 High-Speed SD Mode
    17. 9.17 Serial ATA Controller (SATA)
      1. 9.17.1 SATA Interface Design Specifications
        1. 9.17.1.1 SATA Interface Schematic
        2. 9.17.1.2 Compatible SATA Components and Modes
        3. 9.17.1.3 PCB Stackup Specifications
        4. 9.17.1.4 Routing Specifications
        5. 9.17.1.5 Coupling Capacitors
      2. 9.17.2 SATA Peripheral Register Descriptions
    18. 9.18 Serial Peripheral Interface (SPI)
      1. 9.18.1 SPI Peripheral Register Descriptions
      2. 9.18.2 SPI Electrical Data and Timing
    19. 9.19 Timers
      1. 9.19.1 Timer Peripheral Register Descriptions
      2. 9.19.2 Timer Electrical Data and Timing
    20. 9.20 Universal Asynchronous Receiver and Transmitter (UART)
      1. 9.20.1 UART Peripheral Register Descriptions
      2. 9.20.2 UART Electrical Data and Timing
    21. 9.21 Universal Serial Bus (USB2.0)
      1. 9.21.1 USB2.0 Peripheral Register Descriptions
      2. 9.21.2 USB2.0 Electrical Data and Timing
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
      2. 10.1.2 Device Speed Range Overview
    2. 10.2 Documentation Support
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CYG|1031
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 System Interconnect

The L3 interconnect allows the sharing of resources, such as peripherals and external or on-chip memories, between all the initiators of the platform. The L4 interconnects control access to the peripherals.

Transfers between initiators and targets across the platform are physically conditioned by the chip interconnect.

7.1 L3 Interconnect

The L3 topology is driven by performance requirements, bus types, and clocking structure. Figure 7-1 shows the interconnect of the device and the main modules and subsystems in the platform. Arrows indicate the master-and-slave relationship, not data flow. Master-and-slave connectivity is shown in Table 7-1.

TMS320DM8168 TMS320DM8167 TMS320DM8165 sys_int_conn_sprs614.gif
A. SGX530 is available only on the DM8168 device.
B. Three HDVICP2 modules are available on the DM8168 and DM8167 devices; two HDVICP2 modules (HDVICP2-0 and HDVICP2-1) are available on the DM8165 devices.
Figure 7-1 Interconnect Overview

Table 7-1 L3 Master-and-Slave Connectivity(1)(2)(3)

MASTERS SLAVES
SYSTEM MMU DMM TILER0 DMM TILER1 DMM ELLA GPMC SGX530 C674x_SDMA PCIe GEN2 SLAVE McASPs McBSP HDMI 1.3 TX AUDIO L4 HS PERIPH PORT 0 L4 HS PERIPH PORT 1 L4 STD PERIPH PORT 0 L4 STD PERIPH PORT 1 EDMA TPTC0 - 3 CFG EDMA TPCC OCMC RAM0 AND RAM1 USB2.0 CFG
ARM Cortex-A8 M1 (128-bit) X
ARM Cortex-A8 M2 (64-bit) X X X X X X X X X X X X X X
C674x MDMA X
System MMU X X X X
C674x CFG X X
HDVICP2-0 VDMA X X
HDVICP2-1 VDMA X X
HDVICP2-2 VDMA X X
HDVPSS Mstr0 X X
HDVPSS Mstr1 X X
SGX530 BIF X
SATA X X
EMAC0 Rx and Tx X X
EMAC1 Rx and Tx X X
USB2.0 DMA X
USB2.0 Queue Mgr X X
PCIe Gen2 X X X X
EDMA TPTC0 S X X X X X X X X X X X
EDMA TPTC1 X X X X X X X X X X X
EDMA TPTC2 X X X X X X X X X X X
EDMA TPTC3 X X X X X X X X X X X
(1) X = Connection exists.
S = Selectable path based on thirty-third address bit from control module register for System MMU accessible targets. Non-System MMU accessible targets (such as C674x SDMA) are always direct mapped.
(2) Three HDVICP2 modules are available on the DM8168 and DM8167 devices; two HDVICP2 modules (HDVICP2-0 and HDVICP2-1) are available on the DM8165 devices.
(3) SGX530 is available only on the DM8168 device.

7.2 L4 Interconnect

The L4 interconnect is a non-blocking peripheral interconnect that provides low-latency access to a large number of low-bandwidth, physically-dispersed target cores. The L4 can handle incoming traffic from up to four initiators and can distribute those communication requests to and collect related responses from up to 63 targets.

The device provides three interfaces with L3 interconnect for high-speed peripheral and standard peripheral.Figure 7-2 and Table 7-2 show the L4 bus architecture and memory-mapped peripherals.

TMS320DM8168 TMS320DM8167 TMS320DM8165 l4_arch_sprs614.gif
A. Three HDVICP2 modules are available on the DM8168 and DM8167 devices; two HDVICP2 modules are available on the DM8165 devices.
B. SGX530 is available only on the DM8168 device.
Figure 7-2 L4 Architecture

Table 7-2 L4 Peripheral Connectivity(1)

L4 PERIPHERALS MASTERS
Cortex-A8 M2 (64-bit) EDMA TPTC0 EDMA TPTC1 EDMA TPTC2 EDMA TPTC3 C674x CONFIG SYSTEM MMU
L4 High-Speed Peripherals Port0 and Port1
EMAC0 Port0 Port1 Port0 Port1 Port0
EMAC1 Port0 Port1 Port0 Port1 Port0
SATA Port0 Port1 Port0 Port1 Port0
L4 Standard-Speed Peripherals Port0 and Port1
I2C0 Port0 Port1 Port0 Port1 Port0
I2C1 Port0 Port1 Port0 Port1 Port0
SPI Port0 Port1 Port0 Port1 Port0
UART0 Port0 Port1 Port0 Port1 Port0
UART1 Port0 Port1 Port0 Port1 Port0
Timer1 Port0 Port1 Port0 Port1 Port0
Timer2 Port0 Port1 Port0 Port1 Port0
Timer3 Port0 Port1 Port0 Port1 Port0
Timer4 Port0 Port1 Port0 Port1 Port0 Port0
Timer5 Port0 Port1 Port0 Port1 Port0 Port0
Timer6 Port0 Port1 Port0 Port1 Port0 Port0
Timer7 Port0 Port1 Port0 Port1 Port0
GPIO0 Port0 Port1 Port0 Port1 Port0
GPIO1 Port0 Port1 Port0 Port1 Port0
SD and SDIO Port0 Port1 Port0 Port1 Port0
WDT Port0 Port1 Port0 Port1 Port0
RTC Port0 Port1 Port0 Port1 Port0
System MMU Port0 Port1 Port0 Port1 Port0
SmartReflex0 Port0
SmartReflex1 Port0
DDR_CFG0 Port0
DDR_CFG1 Port0
Spinlock Port0 Port0 Port0
PRCM Port0
Control and Top Regs Port0
ELM Port0
HDMIphy Port0
OCPWP Port0
McASP0 Port0 Port1 Port0 Port1 Port0
McASP1 Port0 Port1 Port0 Port1 Port0
McASP2 Port0 Port1 Port0 Port1 Port0
Mailbox Port0 Port1 Port0 Port1 Port0 Port0 Port0
(1) X, Port0, Port1 = Connection exists.