SPRSP63B October   2022  – November 2023 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR and ePWM X-BAR
    5. 5.5 GPIO and ADC Allocation
    6. 5.6 Pins With Internal Pullup and Pulldown
    7. 5.7 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Power Consumption Summary
      1. 6.4.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.4.2 System Current Consumption - VREG Disable - External Supply
      3. 6.4.3 Operating Mode Test Description
      4. 6.4.4 Current Consumption Graphs
      5. 6.4.5 Reducing Current Consumption
        1. 6.4.5.1 Typical Current Reduction per Disabled Peripheral
    5. 6.5  Electrical Characteristics
    6. 6.6  Thermal Resistance Characteristics for PM Package
    7. 6.7  Thermal Resistance Characteristics for PT Package
    8. 6.8  Thermal Resistance Characteristics for RGZ Package
    9. 6.9  Thermal Resistance Characteristics for RHB Package
    10. 6.10 Thermal Design Considerations
    11. 6.11 System
      1. 6.11.1  Power Management Module (PMM)
        1. 6.11.1.1 Introduction
        2. 6.11.1.2 Overview
          1. 6.11.1.2.1 Power Rail Monitors
            1. 6.11.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.11.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.11.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.11.1.2.2 External Supervisor Usage
          3. 6.11.1.2.3 Delay Blocks
          4. 6.11.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.11.1.2.5 VREGENZ
        3. 6.11.1.3 External Components
          1. 6.11.1.3.1 Decoupling Capacitors
            1. 6.11.1.3.1.1 VDDIO Decoupling
            2. 6.11.1.3.1.2 VDD Decoupling
        4. 6.11.1.4 Power Sequencing
          1. 6.11.1.4.1 Supply Pins Ganging
          2. 6.11.1.4.2 Signal Pins Power Sequence
          3. 6.11.1.4.3 Supply Pins Power Sequence
            1. 6.11.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.11.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.11.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.11.1.4.3.4 Supply Slew Rate
        5. 6.11.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.11.1.6 Power Management Module Electrical Data and Timing
          1. 6.11.1.6.1 Power Management Module Operating Conditions
          2. 6.11.1.6.2 Power Management Module Characteristics
          3.        Supply Voltages
      2. 6.11.2  Reset Timing
        1. 6.11.2.1 Reset Sources
        2. 6.11.2.2 Reset Electrical Data and Timing
          1. 6.11.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.11.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.11.2.2.3 Reset Timing Diagrams
      3. 6.11.3  Clock Specifications
        1. 6.11.3.1 Clock Sources
        2. 6.11.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.11.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.11.3.2.1.1 Input Clock Frequency
            2. 6.11.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.11.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.11.3.2.1.4 X1 Timing Requirements
            5. 6.11.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.11.3.2.1.6 APLL Characteristics
            7. 6.11.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.11.3.2.1.8 Internal Clock Frequencies
        3. 6.11.3.3 Input Clocks and PLLs
        4. 6.11.3.4 XTAL Oscillator
          1. 6.11.3.4.1 Introduction
          2. 6.11.3.4.2 Overview
            1. 6.11.3.4.2.1 Electrical Oscillator
              1. 6.11.3.4.2.1.1 Modes of Operation
                1. 6.11.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.11.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.11.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.11.3.4.2.2 Quartz Crystal
            3. 6.11.3.4.2.3 GPIO Modes of Operation
          3. 6.11.3.4.3 Functional Operation
            1. 6.11.3.4.3.1 ESR – Effective Series Resistance
            2. 6.11.3.4.3.2 Rneg – Negative Resistance
            3. 6.11.3.4.3.3 Start-up Time
              1. 6.11.3.4.3.3.1 X1/X2 Precondition
            4. 6.11.3.4.3.4 DL – Drive Level
          4. 6.11.3.4.4 How to Choose a Crystal
          5. 6.11.3.4.5 Testing
          6. 6.11.3.4.6 Common Problems and Debug Tips
          7. 6.11.3.4.7 Crystal Oscillator Specifications
            1. 6.11.3.4.7.1 Crystal Oscillator Parameters
            2. 6.11.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.11.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.11.3.5 Internal Oscillators
          1. 6.11.3.5.1 INTOSC Characteristics
          2. 6.11.3.5.2 INTOSC2 with External Precision Resistor – ExtR
      4. 6.11.4  Flash Parameters
        1. 6.11.4.1 Flash Parameters 
      5. 6.11.5  RAM Specifications
      6. 6.11.6  ROM Specifications
      7. 6.11.7  Emulation/JTAG
        1. 6.11.7.1 JTAG Electrical Data and Timing
          1. 6.11.7.1.1 JTAG Timing Requirements
          2. 6.11.7.1.2 JTAG Switching Characteristics
          3. 6.11.7.1.3 JTAG Timing Diagram
        2. 6.11.7.2 cJTAG Electrical Data and Timing
          1. 6.11.7.2.1 cJTAG Timing Requirements
          2. 6.11.7.2.2 cJTAG Switching Characteristics
          3. 6.11.7.2.3 cJTAG Timing Diagram
      8. 6.11.8  GPIO Electrical Data and Timing
        1. 6.11.8.1 GPIO – Output Timing
          1. 6.11.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.11.8.1.2 General-Purpose Output Timing Diagram
        2. 6.11.8.2 GPIO – Input Timing
          1. 6.11.8.2.1 General-Purpose Input Timing Requirements
          2. 6.11.8.2.2 Sampling Mode
        3. 6.11.8.3 Sampling Window Width for Input Signals
      9. 6.11.9  Interrupts
        1. 6.11.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.11.9.1.1 External Interrupt Timing Requirements
          2. 6.11.9.1.2 External Interrupt Switching Characteristics
          3. 6.11.9.1.3 External Interrupt Timing
      10. 6.11.10 Low-Power Modes
        1. 6.11.10.1 Clock-Gating Low-Power Modes
        2. 6.11.10.2 Low-Power Mode Wake-up Timing
          1. 6.11.10.2.1 IDLE Mode Timing Requirements
          2. 6.11.10.2.2 IDLE Mode Switching Characteristics
          3. 6.11.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.11.10.2.4 STANDBY Mode Timing Requirements
          5. 6.11.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.11.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.11.10.2.7 HALT Mode Timing Requirements
          8. 6.11.10.2.8 HALT Mode Switching Characteristics
          9. 6.11.10.2.9 HALT Entry and Exit Timing Diagram
    12. 6.12 Analog Peripherals
      1. 6.12.1 Analog Pins and Internal Connections
      2. 6.12.2 Analog Signal Descriptions
      3. 6.12.3 Analog-to-Digital Converter (ADC)
        1. 6.12.3.1 ADC Configurability
          1. 6.12.3.1.1 Signal Mode
        2. 6.12.3.2 ADC Electrical Data and Timing
          1. 6.12.3.2.1 ADC Operating Conditions
          2. 6.12.3.2.2 ADC Characteristics
          3. 6.12.3.2.3 ADC Performance Per Pin
          4. 6.12.3.2.4 ADC Input Model
          5. 6.12.3.2.5 ADC Timing Diagrams
      4. 6.12.4 Temperature Sensor
        1. 6.12.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.12.4.1.1 Temperature Sensor Characteristics
      5. 6.12.5 Comparator Subsystem (CMPSS)
        1. 6.12.5.1 CMPSS Module Variants
        2. 6.12.5.2 CMPx_DACL
        3. 6.12.5.3 CMPSS Connectivity Diagram
        4. 6.12.5.4 Block Diagrams
        5. 6.12.5.5 CMPSS Electrical Data and Timing
          1. 6.12.5.5.1 CMPSS Comparator Electrical Characteristics
          2. 6.12.5.5.2 CMPSS_LITE Comparator Electrical Characteristics
          3.        CMPSS Comparator Input Referred Offset and Hysteresis
          4. 6.12.5.5.3 CMPSS DAC Static Electrical Characteristics
          5. 6.12.5.5.4 CMPSS_LITE DAC Static Electrical Characteristics
          6. 6.12.5.5.5 CMPSS Illustrative Graphs
          7. 6.12.5.5.6 CMPSS DAC Dynamic Error
          8. 6.12.5.5.7 Buffered Output from CMPx_DACL Operating Conditions
          9. 6.12.5.5.8 Buffered Output from CMPx_DACL Electrical Characteristics
    13. 6.13 Control Peripherals
      1. 6.13.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.13.1.1 Control Peripherals Synchronization
        2. 6.13.1.2 ePWM Electrical Data and Timing
          1. 6.13.1.2.1 ePWM Timing Requirements
          2. 6.13.1.2.2 ePWM Switching Characteristics
          3. 6.13.1.2.3 Trip-Zone Input Timing
            1. 6.13.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.13.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.13.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.13.2.1 HRPWM Electrical Data and Timing
          1. 6.13.2.1.1 High-Resolution PWM Characteristics
      3. 6.13.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.13.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.13.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.13.4 Enhanced Capture (eCAP)
        1. 6.13.4.1 eCAP Block Diagram
        2. 6.13.4.2 eCAP Synchronization
        3. 6.13.4.3 eCAP Electrical Data and Timing
          1. 6.13.4.3.1 eCAP Timing Requirements
          2. 6.13.4.3.2 eCAP Switching Characteristics
      5. 6.13.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.13.5.1 eQEP Electrical Data and Timing
          1. 6.13.5.1.1 eQEP Timing Requirements
          2. 6.13.5.1.2 eQEP Switching Characteristics
    14. 6.14 Communications Peripherals
      1. 6.14.1 Controller Area Network (CAN)
      2. 6.14.2 Inter-Integrated Circuit (I2C)
        1. 6.14.2.1 I2C Electrical Data and Timing
          1. 6.14.2.1.1 I2C Timing Requirements
          2. 6.14.2.1.2 I2C Switching Characteristics
          3. 6.14.2.1.3 I2C Timing Diagram
      3. 6.14.3 Serial Communications Interface (SCI)
      4. 6.14.4 Serial Peripheral Interface (SPI)
        1. 6.14.4.1 SPI Master Mode Timings
          1. 6.14.4.1.1 SPI Master Mode Timing Requirements
          2. 6.14.4.1.2 SPI Master Mode Switching Characteristics - Clock Phase 0
          3. 6.14.4.1.3 SPI Master Mode Switching Characteristics - Clock Phase 1
          4. 6.14.4.1.4 SPI Master Mode Timing Diagrams
        2. 6.14.4.2 SPI Slave Mode Timings
          1. 6.14.4.2.1 SPI Slave Mode Timing Requirements
          2. 6.14.4.2.2 SPI Slave Mode Switching Characteristics
          3. 6.14.4.2.3 SPI Slave Mode Timing Diagrams
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
      2. 7.3.2 Flash Memory Map
      3. 7.3.3 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  C28x Processor
      1. 7.5.1 Floating-Point Unit (FPU)
      2. 7.5.2 Trigonometric Math Unit (TMU)
    6. 7.6  Device Boot Modes
      1. 7.6.1 Device Boot Configurations
        1. 7.6.1.1 Configuring Boot Mode Pins
        2. 7.6.1.2 Configuring Boot Mode Table Options
      2. 7.6.2 GPIO Assignments
    7. 7.7  Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8  Watchdog
    9. 7.9  C28x Timers
    10. 7.10 Dual-Clock Comparator (DCC)
      1. 7.10.1 Features
      2. 7.10.2 Mapping of DCCx Clock Source Inputs
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Applications
        1. 8.3.1.1 Air-conditioner Outdoor Unit
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Air Conditioner Outdoor Unit Resources
        2. 8.3.1.2 Washer and Dryer
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Washer and Dryer Resources
        3. 8.3.1.3 Robotic Lawn Mower
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 Robotic Lawn Mower Resources
        4. 8.3.1.4 Merchant Telecom Rectifiers
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 Merchant Telecom Rectifiers Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PM|64
  • RGZ|48
  • RHB|32
  • PT|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.2 Pin Attributes

Table 5-1 Pin Attributes
SIGNAL NAME MUX POSITION 64 VPM 64 PM 48 RGZ 48 PT 32 RHB PIN TYPE DESCRIPTION
ANALOG
A0 15 15 11 11 7 I ADC-A Input 0
C15 I ADC-C Input 15
CMP1_DACL I CMPSS-1 Low DAC Output
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2
AIO231 0, 4, 8, 12 I Analog Pin Used For Digital Input 231
A1 14 14 10 10 7 I ADC-A Input 1
CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4
CMP1_LP4 I CMPSS-1 Low Comparator Positive Input 4
AIO232 0, 4, 8, 12 I Analog Pin Used For Digital Input 232
A2 9 9 6 6 4 I ADC-A Input 2
C9 I ADC-C Input 9
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0
GPIO224 I/O General-Purpose Input Output 224 This pin also has digital mux functions which are described in the GPIO section of this table.
A3 8 8 5 5 3 I ADC-A Input 3
C5 I ADC-C Input 5
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0
CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3
GPIO242 I/O General-Purpose Input Output 242 This pin also has digital mux functions which are described in the GPIO section of this table.
A4 23 23 19 19 12 I ADC-A Input 4
C14 I ADC-C Input 14
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3
AIO225 0, 4, 8, 12 I Analog Pin Used For Digital Input 225
A5 13 13 9 9 6 I ADC-A Input 5
C2 I ADC-C Input 2
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1
AIO244 0, 4, 8, 12 I Analog Pin Used For Digital Input 244
A6 6 6 4 4 2 I ADC-A Input 6
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2
GPIO228 I/O General-Purpose Input Output 228 This pin also has digital mux functions which are described in the GPIO section of this table.
A7 19 19 15 15 8 I ADC-A Input 7
C3 I ADC-C Input 3
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1
AIO245 0, 4, 8, 12 I Analog Pin Used For Digital Input 245
A8 20 20 16 16 9 I ADC-A Input 8
C11 I ADC-C Input 11
CMP2_HP4 I CMPSS-2 High Comparator Positive Input 4
CMP2_LP4 I CMPSS-2 Low Comparator Positive Input 4
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4
AIO241 0, 4, 8, 12 I Analog Pin Used For Digital Input 241
A10 25 25 21 21 13 I ADC-A Input 10
C10 I ADC-C Input 10
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3
GPIO230 I/O General-Purpose Input Output 230 This pin also has digital mux functions which are described in the GPIO section of this table.
A11 12 12 8 8 6 I ADC-A Input 11
C0 I ADC-C Input 0
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1
AIO237 0, 4, 8, 12 I Analog Pin Used For Digital Input 237
A12 18 18 14 14 8 I ADC-A Input 12
C1 I ADC-C Input 1
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2
AIO238 0, 4, 8, 12 I Analog Pin Used For Digital Input 238
A15 10 10 7 7 5 I ADC-A Input 15
C7 I ADC-C Input 7
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3
AIO233 0, 4, 8, 12 I Analog Pin Used For Digital Input 233
A16 2 2 2 2 32 I ADC-A Input 16
C16 I ADC-C Input 16
GPIO28 I/O General-Purpose Input Output 28 This pin also has digital mux functions which are described in the GPIO section of this table.
A17 27 27 I ADC-A Input 17
C17 I ADC-C Input 17
GPIO20 I/O General-Purpose Input Output 20 This pin also has digital mux functions which are described in the GPIO section of this table.
A18 28 28 I ADC-A Input 18
C18 I ADC-C Input 18
GPIO21 I/O General-Purpose Input Output 21 This pin also has digital mux functions which are described in the GPIO section of this table.
A19 29 29 22 23 I ADC-A Input 19
C19 I ADC-C Input 19
GPIO13 I/O General-Purpose Input Output 13 This pin also has digital mux functions which are described in the GPIO section of this table.
A20 30 30 23 24 I ADC-A Input 20
C20 I ADC-C Input 20
GPIO12 I/O General-Purpose Input Output 12 This pin also has digital mux functions which are described in the GPIO section of this table.
A14 11 11 7 7 5 I ADC-A Input 14
C4 I ADC-C Input 4
CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4
CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4
AIO239 0, 4, 8, 12 I Analog Pin Used For Digital Input 239
C6 7 7 4 4 2 I ADC-C Input 6
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0
CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0
GPIO226 I/O General-Purpose Input Output 226 This pin also has digital mux functions which are described in the GPIO section of this table.
A9 24 24 20 20 13 I ADC-A Input 9
C8 I ADC-C Input 8
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0
GPIO227 I/O General-Purpose Input Output 227 This pin also has digital mux functions which are described in the GPIO section of this table.
VREFHI 16 16 12 12 I ADC- High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins. On the 32 RHB package, VREFHI is internally tied to VDDA.
VREFLO 17 17 13 13 I ADC- Low Reference
GPIO
GPIO0 0, 4, 8, 12 52 52 41 42 28 I/O General-Purpose Input Output 0
EPWM1_A 1 O ePWM-1 Output A
CANA_RX 2 I CAN-A Receive
OUTPUTXBAR7 3 O Output X-BAR Output 7
SCIA_RX 5 I SCI-A Receive Data
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE)
EQEP1_INDEX 13 I/O eQEP-1 Index
EPWM3_A 15 O ePWM-3 Output A
GPIO1 0, 4, 8, 12 51 51 40 41 27 I/O General-Purpose Input Output 1
EPWM1_B 1 O ePWM-1 Output B
SCIA_TX 5 O SCI-A Transmit Data
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SPIA_SOMI 7 I/O SPI-A Slave Out, Master In (SOMI)
EQEP1_STROBE 9 I/O eQEP-1 Strobe
EPWM3_B 15 O ePWM-3 Output B
GPIO2 0, 4, 8, 12 50 50 39 40 I/O General-Purpose Input Output 2
EPWM2_A 1 O ePWM-2 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
SPIA_SIMO 7 I/O SPI-A Slave In, Master Out (SIMO)
SCIA_TX 9 O SCI-A Transmit Data
I2CB_SDA 11 I/OD I2C-B Open-Drain Bidirectional Data
CANA_TX 14 O CAN-A Transmit
EPWM4_A 15 O ePWM-4 Output A
GPIO3 0, 4, 8, 12 49 49 38 39 26 I/O General-Purpose Input Output 3
EPWM2_B 1 O ePWM-2 Output B
OUTPUTXBAR2 2, 5 O Output X-BAR Output 2
SPIA_CLK 7 I/O SPI-A Clock
SCIA_RX 9 I SCI-A Receive Data
I2CB_SCL 11 I/OD I2C-B Open-Drain Bidirectional Clock
CANA_RX 14 I CAN-A Receive
EPWM4_B 15 O ePWM-4 Output B
GPIO4 0, 4, 8, 12 48 48 37 38 25 I/O General-Purpose Input Output 4
EPWM3_A 1 O ePWM-3 Output A
I2CA_SCL 2 I/OD I2C-A Open-Drain Bidirectional Clock
OUTPUTXBAR3 5 O Output X-BAR Output 3
CANA_TX 6 O CAN-A Transmit
SPIA_SOMI 14 I/O SPI-A Slave Out, Master In (SOMI)
EPWM1_A 15 O ePWM-1 Output A
GPIO5 0, 4, 8, 12 61 61 46 47 30 I/O General-Purpose Input Output 5
EPWM3_B 1 O ePWM-3 Output B
I2CA_SDA 2 I/OD I2C-A Open-Drain Bidirectional Data
OUTPUTXBAR3 3 O Output X-BAR Output 3
CANA_RX 6 I CAN-A Receive
SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE)
SCIA_RX 11 I SCI-A Receive Data
EPWM1_B 15 O ePWM-1 Output B
GPIO6 0, 4, 8, 12 64 64 48 48 I/O General-Purpose Input Output 6
EPWM4_A 1 O ePWM-4 Output A
OUTPUTXBAR4 2 O Output X-BAR Output 4
SYNCOUT 3 O External ePWM Synchronization Pulse
EQEP1_A 5 I eQEP-1 Input A
EPWM2_A 15 O ePWM-2 Output A
GPIO7 0, 4, 8, 12 57 57 43 43 29 I/O General-Purpose Input Output 7
EPWM4_B 1 O ePWM-4 Output B
EPWM2_A 2 O ePWM-2 Output A
OUTPUTXBAR5 3 O Output X-BAR Output 5
EQEP1_B 5 I eQEP-1 Input B
SPIA_SIMO 7 I/O SPI-A Slave In, Master Out (SIMO)
SCIA_TX 11 O SCI-A Transmit Data
CANA_TX 14 O CAN-A Transmit
EPWM2_B 15 O ePWM-2 Output B
GPIO8 0, 4, 8, 12 47 47 36 I/O General-Purpose Input Output 8
EPWM5_A 1 O ePWM-5 Output A
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIA_TX 6 O SCI-A Transmit Data
SPIA_SIMO 7 I/O SPI-A Slave In, Master Out (SIMO)
I2CA_SCL 9 I/OD I2C-A Open-Drain Bidirectional Clock
GPIO9 0, 4, 8, 12 62 62 47 I/O General-Purpose Input Output 9
EPWM5_B 1 O ePWM-5 Output B
SCIB_TX 2 O SCI-B Transmit Data
OUTPUTXBAR6 3 O Output X-BAR Output 6
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIA_RX 6 I SCI-A Receive Data
SPIA_CLK 7 I/O SPI-A Clock
I2CB_SCL 14 I/OD I2C-B Open-Drain Bidirectional Clock
GPIO10 0, 4, 8, 12 63 63 I/O General-Purpose Input Output 10
EPWM6_A 1 O ePWM-6 Output A
ADCSOCBO 3 O ADC Start of Conversion B for External ADC
EQEP1_A 5 I eQEP-1 Input A
SCIB_TX 6 O SCI-B Transmit Data
SPIA_SOMI 7 I/O SPI-A Slave Out, Master In (SOMI)
I2CA_SDA 9 I/OD I2C-A Open-Drain Bidirectional Data
GPIO11 0, 4, 8, 12 31 31 14 I/O General-Purpose Input Output 11
EPWM6_B 1 O ePWM-6 Output B
CANA_RX 2 I CAN-A Receive
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_B 5 I eQEP-1 Input B
SCIB_RX 6 I SCI-B Receive Data
SPIA_STE 7 I/O SPI-A Slave Transmit Enable (STE)
SPIA_SIMO 13 I/O SPI-A Slave In, Master Out (SIMO)
GPIO12 0, 4, 8, 12 30 30 23 24 I/O General-Purpose Input Output 12 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM7_A 1 O ePWM-7 Output A
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIB_TX 6 O SCI-B Transmit Data
SPIA_CLK 11 I/O SPI-A Clock
CANA_RX 13 I CAN-A Receive
GPIO13 0, 4, 8, 12 29 29 22 23 I/O General-Purpose Input Output 13 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM7_B 1 O ePWM-7 Output B
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIB_RX 6 I SCI-B Receive Data
SPIA_SOMI 11 I/O SPI-A Slave Out, Master In (SOMI)
CANA_TX 13 O CAN-A Transmit
GPIO16 0, 4, 8, 12 33 33 25 26 I/O General-Purpose Input Output 16
SPIA_SIMO 1 I/O SPI-A Slave In, Master Out (SIMO)
OUTPUTXBAR7 3 O Output X-BAR Output 7
EPWM5_A 5 O ePWM-5 Output A
SCIA_TX 6 O SCI-A Transmit Data
EQEP1_STROBE 9 I/O eQEP-1 Strobe
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
GPIO17 0, 4, 8, 12 34 34 I/O General-Purpose Input Output 17
SPIA_SOMI 1 I/O SPI-A Slave Out, Master In (SOMI)
OUTPUTXBAR8 3 O Output X-BAR Output 8
EPWM5_B 5 O ePWM-5 Output B
SCIA_RX 6 I SCI-A Receive Data
EQEP1_INDEX 9 I/O eQEP-1 Index
CANA_TX 11 O CAN-A Transmit
EPWM6_A 14 O ePWM-6 Output A
GPIO18 0, 4, 8, 12 41 41 32 33 21 I/O General-Purpose Input Output 18
SPIA_CLK 1 I/O SPI-A Clock
SCIB_TX 2 O SCI-B Transmit Data
CANA_RX 3 I CAN-A Receive
EPWM6_A 5 O ePWM-6 Output A
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
XCLKOUT 11 O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
X2 ALT I/O Crystal oscillator output.
GPIO19 0, 4, 8, 12 42 42 33 34 22 I/O General-Purpose Input Output 19
SPIA_STE 1 I/O SPI-A Slave Transmit Enable (STE)
SCIB_RX 2 I SCI-B Receive Data
CANA_TX 3 O CAN-A Transmit
EPWM6_B 5 O ePWM-6 Output B
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
X1 ALT I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock.
ExtR ALT2 I External resistor for internal oscillator. This can be used for greater clock accuracy.
GPIO20 0, 4, 8, 12 27 27 I/O General-Purpose Input Output 20 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP1_A 1 I eQEP-1 Input A
CANA_TX 3 O CAN-A Transmit
SPIA_SIMO 6 I/O SPI-A Slave In, Master Out (SIMO)
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
SCIC_TX 15 O SCI-C Transmit Data
GPIO21 0, 4, 8, 12 28 28 I/O General-Purpose Input Output 21 This pin also has analog functions which are described in the ANALOG section of this table.
EQEP1_B 1 I eQEP-1 Input B
CANA_RX 3 I CAN-A Receive
SPIA_SOMI 6 I/O SPI-A Slave Out, Master In (SOMI)
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
SCIC_RX 15 I SCI-C Receive Data
GPIO22 0, 4, 8, 12 56 56 I/O General-Purpose Input Output 22
EQEP1_STROBE 1 I/O eQEP-1 Strobe
SCIB_TX 3 O SCI-B Transmit Data
SCIC_TX 9 O SCI-C Transmit Data
EPWM4_A 14 O ePWM-4 Output A
GPIO23 0, 4, 8, 12 54 54 42 I/O General-Purpose Input Output 23
EQEP1_INDEX 1 I/O eQEP-1 Index
SCIB_RX 3 I SCI-B Receive Data
SCIC_RX 9 I SCI-C Receive Data
EPWM4_B 14 O ePWM-4 Output B
GPIO24 0, 4, 8, 12 35 35 26 27 15 I/O General-Purpose Input Output 24
OUTPUTXBAR1 1 O Output X-BAR Output 1
SPIA_STE 3 I/O SPI-A Slave Transmit Enable (STE)
EPWM4_A 5 O ePWM-4 Output A
SPIA_SIMO 6 I/O SPI-A Slave In, Master Out (SIMO)
SCIA_TX 11 O SCI-A Transmit Data
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
GPIO28 0, 4, 8, 12 2 2 2 2 32 I/O General-Purpose Input Output 28 This pin also has analog functions which are described in the ANALOG section of this table.
SCIA_RX 1 I SCI-A Receive Data
EPWM7_A 3 O ePWM-7 Output A
OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP1_A 6 I eQEP-1 Input A
SCIC_TX 10 O SCI-C Transmit Data
SPIA_CLK 11 I/O SPI-A Clock
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data
GPIO29 0, 4, 8, 12 1 1 1 1 31 I/O General-Purpose Input Output 29
SCIA_TX 1 O SCI-A Transmit Data
EPWM7_B 3 O ePWM-7 Output B
OUTPUTXBAR6 5 O Output X-BAR Output 6
EQEP1_B 6 I eQEP-1 Input B
SCIC_RX 10 I SCI-C Receive Data
SPIA_STE 11 I/O SPI-A Slave Transmit Enable (STE)
ERRORSTS 13 O Error Status Output. This signal requires an external pulldown.
I2CB_SCL 14 I/OD I2C-B Open-Drain Bidirectional Clock
GPIO32 0, 4, 8, 12 40 40 31 32 20 I/O General-Purpose Input Output 32
I2CA_SDA 1 I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_INDEX 2 I/O eQEP-1 Index
SPIA_CLK 3 I/O SPI-A Clock
EPWM4_B 5 O ePWM-4 Output B
SCIC_TX 6 O SCI-C Transmit Data
CANA_TX 10 O CAN-A Transmit
ADCSOCBO 13 O ADC Start of Conversion B for External ADC
GPIO33 0, 4, 8, 12 32 32 24 25 I/O General-Purpose Input Output 33
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
OUTPUTXBAR4 5 O Output X-BAR Output 4
SCIC_RX 6 I SCI-C Receive Data
CANA_RX 10 I CAN-A Receive
ADCSOCAO 13 O ADC Start of Conversion A for External ADC
GPIO35 0, 4, 8, 12 39 39 30 31 19 I/O General-Purpose Input Output 35
SCIA_RX 1 I SCI-A Receive Data
SPIA_SOMI 2 I/O SPI-A Slave Out, Master In (SOMI)
I2CA_SDA 3 I/OD I2C-A Open-Drain Bidirectional Data
CANA_RX 5 I CAN-A Receive
SCIC_RX 7 I SCI-C Receive Data
EQEP1_A 9 I eQEP-1 Input A
EPWM5_B 11 O ePWM-5 Output B
TDI 15 I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input.
GPIO37 0, 4, 8, 12 37 37 28 29 17 I/O General-Purpose Input Output 37
OUTPUTXBAR2 1 O Output X-BAR Output 2
SPIA_STE 2 I/O SPI-A Slave Transmit Enable (STE)
I2CA_SCL 3 I/OD I2C-A Open-Drain Bidirectional Clock
SCIA_TX 5 O SCI-A Transmit Data
CANA_TX 6 O CAN-A Transmit
SCIC_TX 7 O SCI-C Transmit Data
EQEP1_B 9 I eQEP-1 Input B
EPWM5_A 11 O ePWM-5 Output A
TDO 15 O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input.
GPIO39 0, 4, 8, 12 46 I/O General-Purpose Input Output 39
SYNCOUT 13 O External ePWM Synchronization Pulse
EQEP1_INDEX 14 I/O eQEP-1 Index
GPIO40 0, 4, 8, 12 53 53 I/O General-Purpose Input Output 40
EPWM2_B 5 O ePWM-2 Output B
SCIB_TX 9 O SCI-B Transmit Data
EQEP1_A 10 I eQEP-1 Input A
GPIO41 0, 4, 8, 12 55 55 I/O General-Purpose Input Output 41
EPWM7_A 1 O ePWM-7 Output A
EPWM2_A 5 O ePWM-2 Output A
SCIB_RX 9 I SCI-B Receive Data
EQEP1_B 10 I eQEP-1 Input B
GPIO224 0, 4, 8, 12 9 9 6 6 4 I/O General-Purpose Input Output 224 This pin also has analog functions which are described in the ANALOG section of this table.
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIA_SIMO 6 I/O SPI-A Slave In, Master Out (SIMO)
EPWM1_A 9 O ePWM-1 Output A
CANA_TX 10 O CAN-A Transmit
EQEP1_A 11 I eQEP-1 Input A
SCIC_TX 14 O SCI-C Transmit Data
GPIO226 0, 4, 8, 12 7 7 4 4 2 I/O General-Purpose Input Output 226 This pin also has analog functions which are described in the ANALOG section of this table.
EPWM6_A 5 O ePWM-6 Output A
SPIA_CLK 6 I/O SPI-A Clock
EPWM1_B 9 O ePWM-1 Output B
EQEP1_STROBE 11 I/O eQEP-1 Strobe
SCIC_RX 14 I SCI-C Receive Data
GPIO227 0, 4, 8, 12 24 24 20 20 13 I/O General-Purpose Input Output 227 This pin also has analog functions which are described in the ANALOG section of this table.
I2CB_SCL 1 I/OD I2C-B Open-Drain Bidirectional Clock
EPWM3_A 3 O ePWM-3 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
EPWM2_B 6 O ePWM-2 Output B
GPIO228 0, 4, 8, 12 6 6 4 4 2 I/O General-Purpose Input Output 228 This pin also has analog functions which are described in the ANALOG section of this table.
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
CANA_TX 5 O CAN-A Transmit
SPIA_SOMI 6 I/O SPI-A Slave Out, Master In (SOMI)
EPWM2_B 9 O ePWM-2 Output B
EQEP1_B 11 I eQEP-1 Input B
GPIO230 0, 4, 8, 12 25 25 21 21 13 I/O General-Purpose Input Output 230 This pin also has analog functions which are described in the ANALOG section of this table.
I2CB_SDA 1 I/OD I2C-B Open-Drain Bidirectional Data
EPWM3_B 3 O ePWM-3 Output B
CANA_RX 5 I CAN-A Receive
EPWM2_A 6 O ePWM-2 Output A
I2CA_SDA 7 I/OD I2C-A Open-Drain Bidirectional Data
GPIO242 0, 4, 8, 12 8 8 5 5 3 I/O General-Purpose Input Output 242 This pin also has analog functions which are described in the ANALOG section of this table.
OUTPUTXBAR2 5 O Output X-BAR Output 2
SPIA_STE 6 I/O SPI-A Slave Transmit Enable (STE)
EPWM4_A 9 O ePWM-4 Output A
CANA_RX 10 I CAN-A Receive
EQEP1_INDEX 11 I/O eQEP-1 Index
TEST, JTAG, AND RESET
TCK 36 36 27 28 16 I JTAG test clock with internal pullup.
TMS 38 38 29 30 18 I/O JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. This device does not have a TRSTn pin. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation.
XRSn 3 3 3 3 1 I/OD Device Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. This pin is an open-drain output with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
POWER AND GROUND
VDD 4, 44, 59 4, 44, 59 35, 44 36, 45 24 1.2-V Digital Logic Power Pins. TI recommends placing a decoupling capacitor near each VDD pin with a total capacitance of approximately 10 µF.
VDDA 22 22 18 18 11 3.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor on each pin. On the 32 RHB package, VREFHI is internally tied to VDDA.
VDDIO 43, 60 43, 60 34, 45 35, 46 23 3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF decoupling capacitor on each pin.
VREGENZ 46 I Internal voltage regulator enable with internal pulldown. Tie low to VSS to enable internal VREG. Tie high to VDDIO to use an external supply.
VSS 5, 26, 45, 58 5, 26, 45, 58 PAD 22, 37, 44 PAD Digital Ground. For QFN packages, the ground pad on the bottom of the package must be soldered to the ground plane of the PCB.
VSSA 21 21 17 17 10 Analog Ground