SPRSP63B October   2022  – November 2023 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR and ePWM X-BAR
    5. 5.5 GPIO and ADC Allocation
    6. 5.6 Pins With Internal Pullup and Pulldown
    7. 5.7 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Power Consumption Summary
      1. 6.4.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.4.2 System Current Consumption - VREG Disable - External Supply
      3. 6.4.3 Operating Mode Test Description
      4. 6.4.4 Current Consumption Graphs
      5. 6.4.5 Reducing Current Consumption
        1. 6.4.5.1 Typical Current Reduction per Disabled Peripheral
    5. 6.5  Electrical Characteristics
    6. 6.6  Thermal Resistance Characteristics for PM Package
    7. 6.7  Thermal Resistance Characteristics for PT Package
    8. 6.8  Thermal Resistance Characteristics for RGZ Package
    9. 6.9  Thermal Resistance Characteristics for RHB Package
    10. 6.10 Thermal Design Considerations
    11. 6.11 System
      1. 6.11.1  Power Management Module (PMM)
        1. 6.11.1.1 Introduction
        2. 6.11.1.2 Overview
          1. 6.11.1.2.1 Power Rail Monitors
            1. 6.11.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.11.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.11.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.11.1.2.2 External Supervisor Usage
          3. 6.11.1.2.3 Delay Blocks
          4. 6.11.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.11.1.2.5 VREGENZ
        3. 6.11.1.3 External Components
          1. 6.11.1.3.1 Decoupling Capacitors
            1. 6.11.1.3.1.1 VDDIO Decoupling
            2. 6.11.1.3.1.2 VDD Decoupling
        4. 6.11.1.4 Power Sequencing
          1. 6.11.1.4.1 Supply Pins Ganging
          2. 6.11.1.4.2 Signal Pins Power Sequence
          3. 6.11.1.4.3 Supply Pins Power Sequence
            1. 6.11.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.11.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.11.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.11.1.4.3.4 Supply Slew Rate
        5. 6.11.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.11.1.6 Power Management Module Electrical Data and Timing
          1. 6.11.1.6.1 Power Management Module Operating Conditions
          2. 6.11.1.6.2 Power Management Module Characteristics
          3.        Supply Voltages
      2. 6.11.2  Reset Timing
        1. 6.11.2.1 Reset Sources
        2. 6.11.2.2 Reset Electrical Data and Timing
          1. 6.11.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.11.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.11.2.2.3 Reset Timing Diagrams
      3. 6.11.3  Clock Specifications
        1. 6.11.3.1 Clock Sources
        2. 6.11.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.11.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.11.3.2.1.1 Input Clock Frequency
            2. 6.11.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.11.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.11.3.2.1.4 X1 Timing Requirements
            5. 6.11.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.11.3.2.1.6 APLL Characteristics
            7. 6.11.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.11.3.2.1.8 Internal Clock Frequencies
        3. 6.11.3.3 Input Clocks and PLLs
        4. 6.11.3.4 XTAL Oscillator
          1. 6.11.3.4.1 Introduction
          2. 6.11.3.4.2 Overview
            1. 6.11.3.4.2.1 Electrical Oscillator
              1. 6.11.3.4.2.1.1 Modes of Operation
                1. 6.11.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.11.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.11.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.11.3.4.2.2 Quartz Crystal
            3. 6.11.3.4.2.3 GPIO Modes of Operation
          3. 6.11.3.4.3 Functional Operation
            1. 6.11.3.4.3.1 ESR – Effective Series Resistance
            2. 6.11.3.4.3.2 Rneg – Negative Resistance
            3. 6.11.3.4.3.3 Start-up Time
              1. 6.11.3.4.3.3.1 X1/X2 Precondition
            4. 6.11.3.4.3.4 DL – Drive Level
          4. 6.11.3.4.4 How to Choose a Crystal
          5. 6.11.3.4.5 Testing
          6. 6.11.3.4.6 Common Problems and Debug Tips
          7. 6.11.3.4.7 Crystal Oscillator Specifications
            1. 6.11.3.4.7.1 Crystal Oscillator Parameters
            2. 6.11.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.11.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.11.3.5 Internal Oscillators
          1. 6.11.3.5.1 INTOSC Characteristics
          2. 6.11.3.5.2 INTOSC2 with External Precision Resistor – ExtR
      4. 6.11.4  Flash Parameters
        1. 6.11.4.1 Flash Parameters 
      5. 6.11.5  RAM Specifications
      6. 6.11.6  ROM Specifications
      7. 6.11.7  Emulation/JTAG
        1. 6.11.7.1 JTAG Electrical Data and Timing
          1. 6.11.7.1.1 JTAG Timing Requirements
          2. 6.11.7.1.2 JTAG Switching Characteristics
          3. 6.11.7.1.3 JTAG Timing Diagram
        2. 6.11.7.2 cJTAG Electrical Data and Timing
          1. 6.11.7.2.1 cJTAG Timing Requirements
          2. 6.11.7.2.2 cJTAG Switching Characteristics
          3. 6.11.7.2.3 cJTAG Timing Diagram
      8. 6.11.8  GPIO Electrical Data and Timing
        1. 6.11.8.1 GPIO – Output Timing
          1. 6.11.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.11.8.1.2 General-Purpose Output Timing Diagram
        2. 6.11.8.2 GPIO – Input Timing
          1. 6.11.8.2.1 General-Purpose Input Timing Requirements
          2. 6.11.8.2.2 Sampling Mode
        3. 6.11.8.3 Sampling Window Width for Input Signals
      9. 6.11.9  Interrupts
        1. 6.11.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.11.9.1.1 External Interrupt Timing Requirements
          2. 6.11.9.1.2 External Interrupt Switching Characteristics
          3. 6.11.9.1.3 External Interrupt Timing
      10. 6.11.10 Low-Power Modes
        1. 6.11.10.1 Clock-Gating Low-Power Modes
        2. 6.11.10.2 Low-Power Mode Wake-up Timing
          1. 6.11.10.2.1 IDLE Mode Timing Requirements
          2. 6.11.10.2.2 IDLE Mode Switching Characteristics
          3. 6.11.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.11.10.2.4 STANDBY Mode Timing Requirements
          5. 6.11.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.11.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.11.10.2.7 HALT Mode Timing Requirements
          8. 6.11.10.2.8 HALT Mode Switching Characteristics
          9. 6.11.10.2.9 HALT Entry and Exit Timing Diagram
    12. 6.12 Analog Peripherals
      1. 6.12.1 Analog Pins and Internal Connections
      2. 6.12.2 Analog Signal Descriptions
      3. 6.12.3 Analog-to-Digital Converter (ADC)
        1. 6.12.3.1 ADC Configurability
          1. 6.12.3.1.1 Signal Mode
        2. 6.12.3.2 ADC Electrical Data and Timing
          1. 6.12.3.2.1 ADC Operating Conditions
          2. 6.12.3.2.2 ADC Characteristics
          3. 6.12.3.2.3 ADC Performance Per Pin
          4. 6.12.3.2.4 ADC Input Model
          5. 6.12.3.2.5 ADC Timing Diagrams
      4. 6.12.4 Temperature Sensor
        1. 6.12.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.12.4.1.1 Temperature Sensor Characteristics
      5. 6.12.5 Comparator Subsystem (CMPSS)
        1. 6.12.5.1 CMPSS Module Variants
        2. 6.12.5.2 CMPx_DACL
        3. 6.12.5.3 CMPSS Connectivity Diagram
        4. 6.12.5.4 Block Diagrams
        5. 6.12.5.5 CMPSS Electrical Data and Timing
          1. 6.12.5.5.1 CMPSS Comparator Electrical Characteristics
          2. 6.12.5.5.2 CMPSS_LITE Comparator Electrical Characteristics
          3.        CMPSS Comparator Input Referred Offset and Hysteresis
          4. 6.12.5.5.3 CMPSS DAC Static Electrical Characteristics
          5. 6.12.5.5.4 CMPSS_LITE DAC Static Electrical Characteristics
          6. 6.12.5.5.5 CMPSS Illustrative Graphs
          7. 6.12.5.5.6 CMPSS DAC Dynamic Error
          8. 6.12.5.5.7 Buffered Output from CMPx_DACL Operating Conditions
          9. 6.12.5.5.8 Buffered Output from CMPx_DACL Electrical Characteristics
    13. 6.13 Control Peripherals
      1. 6.13.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.13.1.1 Control Peripherals Synchronization
        2. 6.13.1.2 ePWM Electrical Data and Timing
          1. 6.13.1.2.1 ePWM Timing Requirements
          2. 6.13.1.2.2 ePWM Switching Characteristics
          3. 6.13.1.2.3 Trip-Zone Input Timing
            1. 6.13.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.13.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.13.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.13.2.1 HRPWM Electrical Data and Timing
          1. 6.13.2.1.1 High-Resolution PWM Characteristics
      3. 6.13.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.13.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.13.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.13.4 Enhanced Capture (eCAP)
        1. 6.13.4.1 eCAP Block Diagram
        2. 6.13.4.2 eCAP Synchronization
        3. 6.13.4.3 eCAP Electrical Data and Timing
          1. 6.13.4.3.1 eCAP Timing Requirements
          2. 6.13.4.3.2 eCAP Switching Characteristics
      5. 6.13.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.13.5.1 eQEP Electrical Data and Timing
          1. 6.13.5.1.1 eQEP Timing Requirements
          2. 6.13.5.1.2 eQEP Switching Characteristics
    14. 6.14 Communications Peripherals
      1. 6.14.1 Controller Area Network (CAN)
      2. 6.14.2 Inter-Integrated Circuit (I2C)
        1. 6.14.2.1 I2C Electrical Data and Timing
          1. 6.14.2.1.1 I2C Timing Requirements
          2. 6.14.2.1.2 I2C Switching Characteristics
          3. 6.14.2.1.3 I2C Timing Diagram
      3. 6.14.3 Serial Communications Interface (SCI)
      4. 6.14.4 Serial Peripheral Interface (SPI)
        1. 6.14.4.1 SPI Master Mode Timings
          1. 6.14.4.1.1 SPI Master Mode Timing Requirements
          2. 6.14.4.1.2 SPI Master Mode Switching Characteristics - Clock Phase 0
          3. 6.14.4.1.3 SPI Master Mode Switching Characteristics - Clock Phase 1
          4. 6.14.4.1.4 SPI Master Mode Timing Diagrams
        2. 6.14.4.2 SPI Slave Mode Timings
          1. 6.14.4.2.1 SPI Slave Mode Timing Requirements
          2. 6.14.4.2.2 SPI Slave Mode Switching Characteristics
          3. 6.14.4.2.3 SPI Slave Mode Timing Diagrams
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
      2. 7.3.2 Flash Memory Map
      3. 7.3.3 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  C28x Processor
      1. 7.5.1 Floating-Point Unit (FPU)
      2. 7.5.2 Trigonometric Math Unit (TMU)
    6. 7.6  Device Boot Modes
      1. 7.6.1 Device Boot Configurations
        1. 7.6.1.1 Configuring Boot Mode Pins
        2. 7.6.1.2 Configuring Boot Mode Table Options
      2. 7.6.2 GPIO Assignments
    7. 7.7  Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8  Watchdog
    9. 7.9  C28x Timers
    10. 7.10 Dual-Clock Comparator (DCC)
      1. 7.10.1 Features
      2. 7.10.2 Mapping of DCCx Clock Source Inputs
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Applications
        1. 8.3.1.1 Air-conditioner Outdoor Unit
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Air Conditioner Outdoor Unit Resources
        2. 8.3.1.2 Washer and Dryer
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Washer and Dryer Resources
        3. 8.3.1.3 Robotic Lawn Mower
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 Robotic Lawn Mower Resources
        4. 8.3.1.4 Merchant Telecom Rectifiers
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 Merchant Telecom Rectifiers Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PM|64
  • RGZ|48
  • RHB|32
  • PT|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.2 Digital Signals

Table 5-3 Digital Signals
SIGNAL NAME PIN TYPE DESCRIPTION GPIO 64 VPM 64 PM 48 RGZ 48 PT 32 RHB
ADCSOCAO O ADC Start of Conversion A for External ADC 8, 33, 228 6, 32, 47 6, 32, 47 4, 24, 36 4, 25 2
ADCSOCBO O ADC Start of Conversion B for External ADC 10, 32 40, 63 40, 63 31 32 20
CANA_RX I CAN-A Receive 0, 3, 5, 11, 12, 18, 21, 33, 35, 230, 242 8, 25, 28, 30, 31, 32, 39, 41, 49, 52, 61 8, 25, 28, 30, 31, 32, 39, 41, 49, 52, 61 5, 21, 23, 24, 30, 32, 38, 41, 46 5, 21, 24, 25, 31, 33, 39, 42, 47 3, 13, 14, 19, 21, 26, 28, 30
CANA_TX O CAN-A Transmit 2, 4, 7, 13, 17, 19, 20, 32, 37, 224, 228 6, 9, 27, 29, 34, 37, 40, 42, 48, 50, 57 6, 9, 27, 29, 34, 37, 40, 42, 48, 50, 57 4, 6, 22, 28, 31, 33, 37, 39, 43 4, 6, 23, 29, 32, 34, 38, 40, 43 2, 4, 17, 20, 22, 25, 29
EPWM1_A O ePWM-1 Output A 0, 4, 224 9, 48, 52 9, 48, 52 6, 37, 41 6, 38, 42 4, 25, 28
EPWM1_B O ePWM-1 Output B 1, 5, 226 7, 51, 61 7, 51, 61 4, 40, 46 4, 41, 47 2, 27, 30
EPWM2_A O ePWM-2 Output A 2, 6, 7, 41, 230 25, 50, 55, 57, 64 25, 50, 55, 57, 64 21, 39, 43, 48 21, 40, 43, 48 13, 29
EPWM2_B O ePWM-2 Output B 3, 7, 40, 227, 228 6, 24, 49, 53, 57 6, 24, 49, 53, 57 4, 20, 38, 43 4, 20, 39, 43 2, 13, 26, 29
EPWM3_A O ePWM-3 Output A 0, 4, 227 24, 48, 52 24, 48, 52 20, 37, 41 20, 38, 42 13, 25, 28
EPWM3_B O ePWM-3 Output B 1, 5, 230 25, 51, 61 25, 51, 61 21, 40, 46 21, 41, 47 13, 27, 30
EPWM4_A O ePWM-4 Output A 2, 6, 22, 24, 242 8, 35, 50, 56, 64 8, 35, 50, 56, 64 5, 26, 39, 48 5, 27, 40, 48 3, 15
EPWM4_B O ePWM-4 Output B 3, 7, 23, 32 40, 49, 54, 57 40, 49, 54, 57 31, 38, 42, 43 32, 39, 43 20, 26, 29
EPWM5_A O ePWM-5 Output A 8, 16, 37 33, 37, 47 33, 37, 47 25, 28, 36 26, 29 17
EPWM5_B O ePWM-5 Output B 9, 17, 35 34, 39, 62 34, 39, 62 30, 47 31 19
EPWM6_A O ePWM-6 Output A 10, 17, 18, 226 7, 34, 41, 63 7, 34, 41, 63 4, 32 4, 33 2, 21
EPWM6_B O ePWM-6 Output B 11, 19 31, 42 31, 42 33 34 14, 22
EPWM7_A O ePWM-7 Output A 12, 28, 41 2, 30, 55 2, 30, 55 2, 23 2, 24 32
EPWM7_B O ePWM-7 Output B 13, 29 1, 29 1, 29 1, 22 1, 23 31
EQEP1_A I eQEP-1 Input A 6, 10, 20, 28, 35, 40, 224 2, 9, 27, 39, 53, 63, 64 2, 9, 27, 39, 53, 63, 64 2, 6, 30, 48 2, 6, 31, 48 4, 19, 32
EQEP1_B I eQEP-1 Input B 7, 11, 21, 29, 37, 41, 228 1, 6, 28, 31, 37, 55, 57 1, 6, 28, 31, 37, 55, 57 1, 4, 28, 43 1, 4, 29, 43 2, 14, 17, 29, 31
EQEP1_INDEX I/O eQEP-1 Index 0, 9, 13, 17, 23, 32, 39, 242 8, 29, 34, 40, 52, 54, 62 8, 29, 34, 40, 46, 52, 54, 62 5, 22, 31, 41, 42, 47 5, 23, 32, 42 3, 20, 28
EQEP1_STROBE I/O eQEP-1 Strobe 1, 8, 12, 16, 22, 226 7, 30, 33, 47, 51, 56 7, 30, 33, 47, 51, 56 4, 23, 25, 36, 40 4, 24, 26, 41 2, 27
ERRORSTS O Error Status Output. This signal requires an external pulldown. 24, 28, 29 1, 2, 35 1, 2, 35 1, 2, 26 1, 2, 27 15, 31, 32
ExtR I External resistor for internal oscillator. This can be used for greater clock accuracy. 19 42 42 33 34 22
GPIO0 I/O General-Purpose Input Output 0 0 52 52 41 42 28
GPIO1 I/O General-Purpose Input Output 1 1 51 51 40 41 27
GPIO2 I/O General-Purpose Input Output 2 2 50 50 39 40
GPIO3 I/O General-Purpose Input Output 3 3 49 49 38 39 26
GPIO4 I/O General-Purpose Input Output 4 4 48 48 37 38 25
GPIO5 I/O General-Purpose Input Output 5 5 61 61 46 47 30
GPIO6 I/O General-Purpose Input Output 6 6 64 64 48 48
GPIO7 I/O General-Purpose Input Output 7 7 57 57 43 43 29
GPIO8 I/O General-Purpose Input Output 8 8 47 47 36
GPIO9 I/O General-Purpose Input Output 9 9 62 62 47
GPIO10 I/O General-Purpose Input Output 10 10 63 63
GPIO11 I/O General-Purpose Input Output 11 11 31 31 14
GPIO12 I/O General-Purpose Input Output 12 12 30 30 23 24
GPIO13 I/O General-Purpose Input Output 13 13 29 29 22 23
GPIO16 I/O General-Purpose Input Output 16 16 33 33 25 26
GPIO17 I/O General-Purpose Input Output 17 17 34 34
GPIO18 I/O General-Purpose Input Output 18 18 41 41 32 33 21
GPIO19 I/O General-Purpose Input Output 19 19 42 42 33 34 22
GPIO20 I/O General-Purpose Input Output 20 20 27 27
GPIO21 I/O General-Purpose Input Output 21 21 28 28
GPIO22 I/O General-Purpose Input Output 22 22 56 56
GPIO23 I/O General-Purpose Input Output 23 23 54 54 42
GPIO24 I/O General-Purpose Input Output 24 24 35 35 26 27 15
GPIO28 I/O General-Purpose Input Output 28 28 2 2 2 2 32
GPIO29 I/O General-Purpose Input Output 29 29 1 1 1 1 31
GPIO32 I/O General-Purpose Input Output 32 32 40 40 31 32 20
GPIO33 I/O General-Purpose Input Output 33 33 32 32 24 25
GPIO35 I/O General-Purpose Input Output 35 35 39 39 30 31 19
GPIO37 I/O General-Purpose Input Output 37 37 37 37 28 29 17
GPIO39 I/O General-Purpose Input Output 39 39 46
GPIO40 I/O General-Purpose Input Output 40 40 53 53
GPIO41 I/O General-Purpose Input Output 41 41 55 55
GPIO224 I/O General-Purpose Input Output 224 224 9 9 6 6 4
GPIO226 I/O General-Purpose Input Output 226 226 7 7 4 4 2
GPIO227 I/O General-Purpose Input Output 227 227 24 24 20 20 13
GPIO228 I/O General-Purpose Input Output 228 228 6 6 4 4 2
GPIO230 I/O General-Purpose Input Output 230 230 25 25 21 21 13
GPIO242 I/O General-Purpose Input Output 242 242 8 8 5 5 3
I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock 1, 4, 8, 18, 20, 33, 37 27, 32, 37, 41, 47, 48, 51 27, 32, 37, 41, 47, 48, 51 24, 28, 32, 36, 37, 40 25, 29, 33, 38, 41 17, 21, 25, 27
I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data 0, 5, 10, 19, 21, 32, 35, 230 25, 28, 39, 40, 42, 52, 61, 63 25, 28, 39, 40, 42, 52, 61, 63 21, 30, 31, 33, 41, 46 21, 31, 32, 34, 42, 47 13, 19, 20, 22, 28, 30
I2CB_SCL I/OD I2C-B Open-Drain Bidirectional Clock 3, 9, 29, 227 1, 24, 49, 62 1, 24, 49, 62 1, 20, 38, 47 1, 20, 39 13, 26, 31
I2CB_SDA I/OD I2C-B Open-Drain Bidirectional Data 2, 28, 230 2, 25, 50 2, 25, 50 2, 21, 39 2, 21, 40 13, 32
OUTPUTXBAR1 O Output X-BAR Output 1 2, 24, 227 24, 35, 50 24, 35, 50 20, 26, 39 20, 27, 40 13, 15
OUTPUTXBAR2 O Output X-BAR Output 2 3, 37, 242 8, 37, 49 8, 37, 49 5, 28, 38 5, 29, 39 3, 17, 26
OUTPUTXBAR3 O Output X-BAR Output 3 4, 5, 224 9, 48, 61 9, 48, 61 6, 37, 46 6, 38, 47 4, 25, 30
OUTPUTXBAR4 O Output X-BAR Output 4 6, 33 32, 64 32, 64 24, 48 25, 48
OUTPUTXBAR5 O Output X-BAR Output 5 7, 28 2, 57 2, 57 2, 43 2, 43 29, 32
OUTPUTXBAR6 O Output X-BAR Output 6 9, 29 1, 62 1, 62 1, 47 1 31
OUTPUTXBAR7 O Output X-BAR Output 7 0, 11, 16 31, 33, 52 31, 33, 52 25, 41 26, 42 14, 28
OUTPUTXBAR8 O Output X-BAR Output 8 17 34 34
SCIA_RX I SCI-A Receive Data 0, 3, 5, 9, 17, 28, 35 2, 34, 39, 49, 52, 61, 62 2, 34, 39, 49, 52, 61, 62 2, 30, 38, 41, 46, 47 2, 31, 39, 42, 47 19, 26, 28, 30, 32
SCIA_TX O SCI-A Transmit Data 1, 2, 7, 8, 16, 24, 29, 37 1, 33, 35, 37, 47, 50, 51, 57 1, 33, 35, 37, 47, 50, 51, 57 1, 25, 26, 28, 36, 39, 40, 43 1, 26, 27, 29, 40, 41, 43 15, 17, 27, 29, 31
SCIB_RX I SCI-B Receive Data 11, 13, 19, 23, 41 29, 31, 42, 54, 55 29, 31, 42, 54, 55 22, 33, 42 23, 34 14, 22
SCIB_TX O SCI-B Transmit Data 9, 10, 12, 18, 22, 40 30, 41, 53, 56, 62, 63 30, 41, 53, 56, 62, 63 23, 32, 47 24, 33 21
SCIC_RX I SCI-C Receive Data 21, 23, 29, 33, 35, 226 1, 7, 28, 32, 39, 54 1, 7, 28, 32, 39, 54 1, 4, 24, 30, 42 1, 4, 25, 31 2, 19, 31
SCIC_TX O SCI-C Transmit Data 20, 22, 28, 32, 37, 224 2, 9, 27, 37, 40, 56 2, 9, 27, 37, 40, 56 2, 6, 28, 31 2, 6, 29, 32 4, 17, 20, 32
SPIA_CLK I/O SPI-A Clock 3, 9, 12, 18, 28, 32, 226 2, 7, 30, 40, 41, 49, 62 2, 7, 30, 40, 41, 49, 62 2, 4, 23, 31, 32, 38, 47 2, 4, 24, 32, 33, 39 2, 20, 21, 26, 32
SPIA_SIMO I/O SPI-A Slave In, Master Out (SIMO) 2, 7, 8, 11, 16, 20, 24, 224 9, 27, 31, 33, 35, 47, 50, 57 9, 27, 31, 33, 35, 47, 50, 57 6, 25, 26, 36, 39, 43 6, 26, 27, 40, 43 4, 14, 15, 29
SPIA_SOMI I/O SPI-A Slave Out, Master In (SOMI) 1, 4, 10, 13, 17, 21, 35, 228 6, 28, 29, 34, 39, 48, 51, 63 6, 28, 29, 34, 39, 48, 51, 63 4, 22, 30, 37, 40 4, 23, 31, 38, 41 2, 19, 25, 27
SPIA_STE I/O SPI-A Slave Transmit Enable (STE) 0, 5, 11, 19, 24, 29, 37, 242 1, 8, 31, 35, 37, 42, 52, 61 1, 8, 31, 35, 37, 42, 52, 61 1, 5, 26, 28, 33, 41, 46 1, 5, 27, 29, 34, 42, 47 3, 14, 15, 17, 22, 28, 30, 31
SYNCOUT O External ePWM Synchronization Pulse 6, 39 64 46, 64 48 48
TDI I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input. 35 39 39 30 31 19
TDO O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input. 37 37 37 28 29 17
X1 I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. 19 42 42 33 34 22
X2 I/O Crystal oscillator output. 18 41 41 32 33 21
XCLKOUT O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. 16, 18 33, 41 33, 41 25, 32 26, 33 21