SPRSP45 Data sheet

SPRSP45C March 2020 – April 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

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PT|48
- MTQF003C

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Orderable Information

6.12.3.2.5 ADC Timing Diagrams

Figure 6-43 shows the ADC conversion timings for two SOCs given the following assumptions:

SOC0 and SOC1 are configured to use the same trigger.
No other SOCs are converting or pending when the trigger occurs.
The round-robin pointer is in a state that causes SOC0 to convert first.
ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).

Table 6-13 lists the descriptions of the ADC timing parameters. Table 6-14 lists the ADC timings.

Figure 6-43 ADC Timings

Table 6-13 ADC Timing Parameters

PARAMETER	DESCRIPTION
t_SH	The duration of the S+H window. At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so t_SH will not necessarily be the same for different SOCs. Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window regardless of device clock settings.
t_LAT	The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register. If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
t_EOC	The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The subsequent sample can start before the conversion results are latched.
t_INT	The time from the end of the S+H window until an ADCINT flag is set (if configured). If the INTPULSEPOS bit in the ADCCTL1 register is set, t_INT will coincide with the conversion results being latched into the result register. If the INTPULSEPOS bit is 0, t_INT will coincide with the end of the S+H window. If t_INT triggers a read of the ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be taken to ensure the read occurs after the results latch (otherwise, the previous results will be read). If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there will be a delay of OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or trigger the DMA at exactly the time the sample is ready.

Table 6-14 ADC Timings

ADCCLK PRESCALE		SYSCLK CYCLES				ADCCLK CYCLES
ADCCTL2 [PRESCALE]	RATIO ADCCLK:SYSCLK	t_EOC	t_LAT⁽¹⁾	t_INT(EARLY)⁽²⁾	t_INT(LATE)	t_EOC
0	1	11	13	1	11	11
2	2	21	23	1	21	10.5
4	3	31	34	1	31	10.3
6	4	41	44	1	41	10.3
8	5	51	55	1	51	10.2
10	6	61	65	1	61	10.2
12	7	71	76	1	71	10.1
14	8	81	86	1	81	10.1

(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F28002x Real-Time MCUs Silicon Errata.

(2) By default, t_INT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET field in the ADCINTCYCLE register.