SPRSP45C March   2020  – April 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins Table
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 GPIO Input X-BAR
      4. 5.4.4 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5.     Supply Voltages
    6. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption
      2. 6.5.2 Operating Mode Test Description
      3. 6.5.3 Current Consumption Graphs
      4. 6.5.4 Reducing Current Consumption
        1. 6.5.4.1 Typical Current Reduction per Disabled Peripheral
    7. 6.6  Electrical Characteristics
    8. 6.7  Thermal Resistance Characteristics for PN Package
    9. 6.8  Thermal Resistance Characteristics for PM Package
    10. 6.9  Thermal Resistance Characteristics for PT Package
    11. 6.10 Thermal Design Considerations
    12. 6.11 System
      1. 6.11.1  Power Management Module (PMM)
        1. 6.11.1.1 Introduction
        2. 6.11.1.2 Overview
          1. 6.11.1.2.1 Power Rail Monitors
            1. 6.11.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.11.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.11.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.11.1.2.2 External Supervisor Usage
          3. 6.11.1.2.3 Delay Blocks
          4. 6.11.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
        3. 6.11.1.3 External Components
          1. 6.11.1.3.1 Decoupling Capacitors
            1. 6.11.1.3.1.1 VDDIO Decoupling
            2. 6.11.1.3.1.2 VDD Decoupling
        4. 6.11.1.4 Power Sequencing
          1. 6.11.1.4.1 Supply Pins Ganging
          2. 6.11.1.4.2 Signal Pins Power Sequence
          3. 6.11.1.4.3 Supply Pins Power Sequence
            1. 6.11.1.4.3.1 Internal VREG/VDD Mode Sequence
            2. 6.11.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 6.11.1.4.3.3 Supply Slew Rate
        5. 6.11.1.5 Power Management Module Electrical Data and Timing
          1. 6.11.1.5.1 Power Management Module Characteristics
          2. 6.11.1.5.2 Power Management Module Operating Conditions
      2. 6.11.2  Reset Timing
        1. 6.11.2.1 Reset Sources
        2. 6.11.2.2 Reset Electrical Data and Timing
          1. 6.11.2.2.1 Reset (XRSn) Timing Requirements
          2. 6.11.2.2.2 Reset (XRSn) Switching Characteristics
          3. 6.11.2.2.3 Reset Timing Diagrams
      3. 6.11.3  Clock Specifications
        1. 6.11.3.1 Clock Sources
        2. 6.11.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.11.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.11.3.2.1.1 Input Clock Frequency
            2. 6.11.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.11.3.2.1.3 X1 Timing Requirements
            4. 6.11.3.2.1.4 APLL Characteristics
            5. 6.11.3.2.1.5 XCLKOUT Switching Characteristics
            6. 6.11.3.2.1.6 Internal Clock Frequencies
        3. 6.11.3.3 Input Clocks and PLLs
        4. 6.11.3.4 XTAL Oscillator
          1. 6.11.3.4.1 Introduction
          2. 6.11.3.4.2 Overview
            1. 6.11.3.4.2.1 Electrical Oscillator
              1. 6.11.3.4.2.1.1 Modes of Operation
                1. 6.11.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.11.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.11.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.11.3.4.2.2 Quartz Crystal
            3. 6.11.3.4.2.3 GPIO Modes of Operation
          3. 6.11.3.4.3 Functional Operation
            1. 6.11.3.4.3.1 ESR – Effective Series Resistance
            2. 6.11.3.4.3.2 Rneg – Negative Resistance
            3. 6.11.3.4.3.3 Start-up Time
            4. 6.11.3.4.3.4 DL – Drive Level
          4. 6.11.3.4.4 How to Choose a Crystal
          5. 6.11.3.4.5 Testing
          6. 6.11.3.4.6 Common Problems and Debug Tips
          7. 6.11.3.4.7 Crystal Oscillator Specifications
            1. 6.11.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.11.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
        5. 6.11.3.5 Internal Oscillators
          1. 6.11.3.5.1 INTOSC Characteristics
      4. 6.11.4  Flash Parameters
      5. 6.11.5  RAM Specifications
      6. 6.11.6  ROM Specifications
      7. 6.11.7  Emulation/JTAG
        1. 6.11.7.1 JTAG Electrical Data and Timing
          1. 6.11.7.1.1 JTAG Timing Requirements
          2. 6.11.7.1.2 JTAG Switching Characteristics
          3. 6.11.7.1.3 JTAG Timing Diagram
        2. 6.11.7.2 cJTAG Electrical Data and Timing
          1. 6.11.7.2.1 cJTAG Timing Requirements
          2. 6.11.7.2.2 cJTAG Switching Characteristics
          3. 6.11.7.2.3 cJTAG Timing Diagram
      8. 6.11.8  GPIO Electrical Data and Timing
        1. 6.11.8.1 GPIO – Output Timing
          1. 6.11.8.1.1 General-Purpose Output Switching Characteristics
        2. 6.11.8.2 GPIO – Input Timing
          1. 6.11.8.2.1 General-Purpose Input Timing Requirements
          2. 6.11.8.2.2 Sampling Mode
        3. 6.11.8.3 Sampling Window Width for Input Signals
      9. 6.11.9  Interrupts
        1. 6.11.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.11.9.1.1 External Interrupt Timing Requirements
          2. 6.11.9.1.2 External Interrupt Switching Characteristics
          3. 6.11.9.1.3 External Interrupt Timing
      10. 6.11.10 Low-Power Modes
        1. 6.11.10.1 Clock-Gating Low-Power Modes
        2. 6.11.10.2 Low-Power Mode Wake-up Timing
          1. 6.11.10.2.1 IDLE Mode Timing Requirements
          2. 6.11.10.2.2 IDLE Mode Switching Characteristics
          3. 6.11.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.11.10.2.4 STANDBY Mode Timing Requirements
          5. 6.11.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.11.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.11.10.2.7 HALT Mode Timing Requirements
          8. 6.11.10.2.8 HALT Mode Switching Characteristics
          9. 6.11.10.2.9 HALT Entry and Exit Timing Diagram
    13. 6.12 Analog Peripherals
      1. 6.12.1 Analog Pins and Internal Connections
      2. 6.12.2 Analog Signal Descriptions
      3. 6.12.3 Analog-to-Digital Converter (ADC)
        1. 6.12.3.1 ADC Configurability
          1. 6.12.3.1.1 Signal Mode
        2. 6.12.3.2 ADC Electrical Data and Timing
          1. 6.12.3.2.1 ADC Operating Conditions
          2. 6.12.3.2.2 ADC Characteristics
          3. 6.12.3.2.3 ADC INL and DNL
          4. 6.12.3.2.4 ADC Input Model
          5. 6.12.3.2.5 ADC Timing Diagrams
      4. 6.12.4 Temperature Sensor
        1. 6.12.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.12.4.1.1 Temperature Sensor Characteristics
      5. 6.12.5 Comparator Subsystem (CMPSS)
        1. 6.12.5.1 CMPSS Electrical Data and Timing
          1. 6.12.5.1.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.12.5.1.2 CMPSS DAC Static Electrical Characteristics
          4. 6.12.5.1.3 CMPSS Illustrative Graphs
    14. 6.13 Control Peripherals
      1. 6.13.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.13.1.1 Control Peripherals Synchronization
        2. 6.13.1.2 ePWM Electrical Data and Timing
          1. 6.13.1.2.1 ePWM Timing Requirements
          2. 6.13.1.2.2 ePWM Switching Characteristics
          3. 6.13.1.2.3 Trip-Zone Input Timing
            1. 6.13.1.2.3.1 Trip-Zone Input Timing Requirements
        3. 6.13.1.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 6.13.1.3.1 External ADC Start-of-Conversion Switching Characteristics
      2. 6.13.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.13.2.1 HRPWM Electrical Data and Timing
          1. 6.13.2.1.1 High-Resolution PWM Characteristics
      3. 6.13.3 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 6.13.3.1 High-Resolution Capture (HRCAP)
        2. 6.13.3.2 eCAP and HRCAP Block Diagram
        3. 6.13.3.3 eCAP/HRCAP Synchronization
        4. 6.13.3.4 eCAP Electrical Data and Timing
          1. 6.13.3.4.1 eCAP Timing Requirements
          2. 6.13.3.4.2 eCAP Switching Characteristics
        5. 6.13.3.5 HRCAP Electrical Data and Timing
          1. 6.13.3.5.1 HRCAP Switching Characteristics
          2. 6.13.3.5.2 HRCAP Figure and Graph
      4. 6.13.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.13.4.1 eQEP Electrical Data and Timing
          1. 6.13.4.1.1 eQEP Timing Requirements
          2. 6.13.4.1.2 eQEP Switching Characteristics
    15. 6.14 Communications Peripherals
      1. 6.14.1 Controller Area Network (CAN)
      2. 6.14.2 Inter-Integrated Circuit (I2C)
        1. 6.14.2.1 I2C Electrical Data and Timing
          1. 6.14.2.1.1 I2C Timing Requirements
          2. 6.14.2.1.2 I2C Switching Characteristics
          3. 6.14.2.1.3 I2C Timing Diagram
      3. 6.14.3 Power Management Bus (PMBus) Interface
        1. 6.14.3.1 PMBus Electrical Data and Timing
          1. 6.14.3.1.1 PMBus Electrical Characteristics
          2. 6.14.3.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.14.3.1.3 PMBus Standard Mode Switching Characteristics
      4. 6.14.4 Serial Communications Interface (SCI)
      5. 6.14.5 Serial Peripheral Interface (SPI)
        1. 6.14.5.1 SPI Master Mode Timings
          1. 6.14.5.1.1 SPI Master Mode Timing Requirements
          2. 6.14.5.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
          3. 6.14.5.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          4. 6.14.5.1.4 SPI Master Mode Timing Diagrams
        2. 6.14.5.2 SPI Slave Mode Timings
          1. 6.14.5.2.1 SPI Slave Mode Timing Requirements
          2. 6.14.5.2.2 SPI Slave Mode Switching Characteristics
          3. 6.14.5.2.3 SPI Slave Mode Timing Diagrams
      6. 6.14.6 Local Interconnect Network (LIN)
      7. 6.14.7 Fast Serial Interface (FSI)
        1. 6.14.7.1 FSI Transmitter
          1. 6.14.7.1.1 FSITX Electrical Data and Timing
            1. 6.14.7.1.1.1 FSITX Switching Characteristics
            2. 6.14.7.1.1.2 FSITX Timings
        2. 6.14.7.2 FSI Receiver
          1. 6.14.7.2.1 FSIRX Electrical Data and Timing
            1. 6.14.7.2.1.1 FSIRX Timing Requirements
            2. 6.14.7.2.1.2 FSIRX Switching Characteristics
            3. 6.14.7.2.1.3 FSIRX Timings
        3. 6.14.7.3 FSI SPI Compatibility Mode
          1. 6.14.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.14.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.14.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 6.14.8 Host Interface Controller (HIC)
        1. 6.14.8.1 HIC Electrical Data and Timing
          1. 6.14.8.1.1 HIC Timing Requirements
          2. 6.14.8.1.2 HIC Switching Characteristics
          3. 6.14.8.1.3 HIC Timing Diagrams
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
      2. 7.3.2 Flash Memory Map
        1. 7.3.2.1 Addresses of Flash Sectors
      3. 7.3.3 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Fast Integer Division Unit
      3. 7.6.3 Trigonometric Math Unit (TMU)
      4. 7.6.4 VCRC Unit
    7. 7.7  Embedded Real-Time Analysis and Diagnostic (ERAD)
    8. 7.8  Background CRC-32 (BGCRC)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Dual Code Security Module
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx (DCC0 and DCC1) Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Key Device Features
    2. 8.2 Application Information
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Servo Drive Control Module
          1. 8.2.1.1.1 System Block Diagram
          2. 8.2.1.1.2 Servo Drive Control Module Resources
        2. 8.2.1.2 Server or Telecom Power Supply Unit (PSU)
          1. 8.2.1.2.1 System Block Diagram
          2. 8.2.1.2.2 Server and Telecom PSU Resources
        3. 8.2.1.3 Merchant Telecom Rectifiers
          1. 8.2.1.3.1 System Block Diagram
          2. 8.2.1.3.2 Merchant Telecom Rectifiers Resources
        4. 8.2.1.4 EV Charging Station Power Module
          1. 8.2.1.4.1 System Block Diagram
          2. 8.2.1.4.2 EV Charging Station Power Module Resources
        5. 8.2.1.5 Air-conditioner Outdoor Unit
          1. 8.2.1.5.1 System Block Diagram
          2. 8.2.1.5.2 Air Conditioner Outdoor Unit Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device and Development Support Tool Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.2 Pin Attributes

Table 5-1 Pin Attributes
SIGNAL NAMEMUX POSITION80 QFP64 QFP48 QFPPIN TYPEDESCRIPTION
ANALOG
A0191511IADC-A Input 0
C15IADC-C Input 15
CMP3_HP2ICMPSS-3 High Comparator Positive Input 2
CMP3_LP2ICMPSS-3 Low Comparator Positive Input 2
AIO2310, 4, 8, 12IAnalog Pin Used For Digital Input 231
HIC_BASESEL115IHIC Base Address Range Select 1
A1181410IAnalog Input
CMP1_HP4ICMPSS-1 High Comparator Positive Input 4
CMP1_LP4ICMPSS-1 Low Comparator Positive Input 4
AIO2320, 4, 8, 12IAnalog Pin Used For Digital Input 232
HIC_BASESEL015IHIC Base Address Range Select 0
A10292521IADC-A Input 10
C10IADC-C Input 10
CMP2_HP3ICMPSS-2 High Comparator Positive Input 3
CMP2_HN0ICMPSS-2 High Comparator Negative Input 0
CMP2_LP3ICMPSS-2 Low Comparator Positive Input 3
CMP2_LN0ICMPSS-2 Low Comparator Negative Input 0
AIO2300, 4, 8, 12IAnalog Pin Used For Digital Input 230
HIC_BASESEL215IHIC Base Address Range Select 2
A1116128IADC-A Input 11
C0IADC-C Input 0
CMP1_HP1ICMPSS-1 High Comparator Positive Input 1
CMP1_HN1ICMPSS-1 High Comparator Negative Input 1
CMP1_LP1ICMPSS-1 Low Comparator Positive Input 1
CMP1_LN1ICMPSS-1 Low Comparator Negative Input 1
AIO2370, 4, 8, 12IAnalog Pin Used For Digital Input 237
HIC_A615IHIC Address 6
A12221814IADC-A Input 12
C1IADC-C Input 1
CMP2_HP1ICMPSS-2 High Comparator Positive Input 1
CMP4_HP2ICMPSS-4 High Comparator Positive Input 2
CMP2_HN1ICMPSS-2 High Comparator Negative Input 1
CMP2_LP1ICMPSS-2 Low Comparator Positive Input 1
CMP4_LP2ICMPSS-4 Low Comparator Positive Input 2
CMP2_LN1ICMPSS-2 Low Comparator Negative Input 1
AIO2380, 4, 8, 12IAnalog Pin Used For Digital Input 238
HIC_NCS15IHIC Chip Select
A141511IADC-A Input 14
C4IADC-C Input 4
CMP3_HP4ICMPSS-3 High Comparator Positive Input 4
CMP3_LP4ICMPSS-3 Low Comparator Positive Input 4
AIO2390, 4, 8, 12IAnalog Pin Used For Digital Input 239
HIC_A515IHIC Address 5
A1514107IADC-A Input 15
C7IADC-C Input 7
CMP1_HP3ICMPSS-1 High Comparator Positive Input 3
CMP1_HN0ICMPSS-1 High Comparator Negative Input 0
CMP1_LP3ICMPSS-1 Low Comparator Positive Input 3
CMP1_LN0ICMPSS-1 Low Comparator Negative Input 0
AIO2330, 4, 8, 12IAnalog Pin Used For Digital Input 233
HIC_A415IHIC Address 4
A21396IADC-A Input 2
C9IADC-C Input 9
CMP1_HP0ICMPSS-1 High Comparator Positive Input 0
CMP1_LP0ICMPSS-1 Low Comparator Positive Input 0
AIO2240, 4, 8, 12IAnalog Pin Used For Digital Input 224
HIC_A315IHIC Address 3
A31285IADC-A Input 3
C5IADC-C Input 5
VDACIOptional external reference voltage for on-chip CMPSS DACs. There is an internal capacitor to VSSA on this pin whether used for ADC input or CMPSS DAC reference which cannot be disabled. If this pin is being used as a reference for the CMPSS DACs, place at least a 1-µF capacitor on this pin.
CMP3_HP3ICMPSS-3 High Comparator Positive Input 3
CMP3_HN0ICMPSS-3 High Comparator Negative Input 0
CMP3_LP3ICMPSS-3 Low Comparator Positive Input 3
CMP3_LN0ICMPSS-3 Low Comparator Negative Input 0
AIO2420, 4, 8, 12IAnalog Pin Used For Digital Input 242
HIC_A215IHIC Address 2
A4272319IADC-A Input 4
C14IADC-C Input 14
CMP2_HP0ICMPSS-2 High Comparator Positive Input 0
CMP4_HP3ICMPSS-4 High Comparator Positive Input 3
CMP4_HN0ICMPSS-4 High Comparator Negative Input 0
CMP2_LP0ICMPSS-2 Low Comparator Positive Input 0
CMP4_LP3ICMPSS-4 Low Comparator Positive Input 3
CMP4_LN0ICMPSS-4 Low Comparator Negative Input 0
AIO2250, 4, 8, 12IAnalog Pin Used For Digital Input 225
HIC_NWE15IHIC Data Write Enable
A517139IADC-A Input 5
C2IADC-C Input 2
CMP3_HP1ICMPSS-3 High Comparator Positive Input 1
CMP3_HN1ICMPSS-3 High Comparator Negative Input 1
CMP3_LP1ICMPSS-3 Low Comparator Positive Input 1
CMP3_LN1ICMPSS-3 Low Comparator Negative Input 1
AIO2440, 4, 8, 12IAnalog Pin Used For Digital Input 244
HIC_A715IHIC Address 7
A61064IAnalog Input
CMP1_HP2ICMPSS-1 High Comparator Positive Input 2
CMP1_LP2ICMPSS-1 Low Comparator Positive Input 2
AIO2280, 4, 8, 12IAnalog Pin Used For Digital Input 228
HIC_A015IHIC Address 0
A7231915IADC-A Input 7
C3IADC-C Input 3
CMP4_HP1ICMPSS-4 High Comparator Positive Input 1
CMP4_HN1ICMPSS-4 High Comparator Negative Input 1
CMP4_LP1ICMPSS-4 Low Comparator Positive Input 1
CMP4_LN1ICMPSS-4 Low Comparator Negative Input 1
AIO2450, 4, 8, 12IAnalog Pin Used For Digital Input 245
HIC_NOE15OHIC Output Enable
A8242016IADC-A Input 8
C11IADC-C Input 11
CMP2_HP4ICMPSS-2 High Comparator Positive Input 4
CMP4_HP4ICMPSS-4 High Comparator Positive Input 4
CMP2_LP4ICMPSS-2 Low Comparator Positive Input 4
CMP4_LP4ICMPSS-4 Low Comparator Positive Input 4
AIO2410, 4, 8, 12IAnalog Pin Used For Digital Input 241
HIC_NBE115IHIC Byte Enable 1
A9282420IADC-A Input 9
C8IADC-C Input 8
CMP2_HP2ICMPSS-2 High Comparator Positive Input 2
CMP4_HP0ICMPSS-4 High Comparator Positive Input 0
CMP2_LP2ICMPSS-2 Low Comparator Positive Input 2
CMP4_LP0ICMPSS-4 Low Comparator Positive Input 0
AIO2270, 4, 8, 12IAnalog Pin Used For Digital Input 227
HIC_NBE015IHIC Byte Enable 0
C61174IAnalog Input
CMP3_HP0ICMPSS-3 High Comparator Positive Input 0
CMP3_LP0ICMPSS-3 Low Comparator Positive Input 0
AIO2260, 4, 8, 12IAnalog Pin Used For Digital Input 226
HIC_A115IHIC Address 1
VREFHI201612IADC- High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins.
VREFLO211713IADC- Low Reference
GPIO
GPIO00, 4, 8, 12635242I/OGeneral-Purpose Input Output 0
EPWM1_A1OePWM-1 Output A
I2CA_SDA6I/ODI2C-A Open-Drain Bidirectional Data
SPIA_STE7I/OSPI-A Slave Transmit Enable (STE)
FSIRXA_CLK9IFSIRX-A Input Clock
CLB_OUTPUTXBAR811OCLB Output X-BAR Output 8
HIC_BASESEL115IHIC Base Address Range Select 1
GPIO10, 4, 8, 12625141I/OGeneral-Purpose Input Output 1
EPWM1_B1OePWM-1 Output B
I2CA_SCL6I/ODI2C-A Open-Drain Bidirectional Clock
SPIA_SOMI7I/OSPI-A Slave Out, Master In (SOMI)
CLB_OUTPUTXBAR711OCLB Output X-BAR Output 7
HIC_A213IHIC Address 2
FSITXA_TDM_D114IFSITX-A Time Division Multiplexed Additional Data Input
HIC_D1015I/OHIC Data 10
GPIO20, 4, 8, 12615040I/OGeneral-Purpose Input Output 2
EPWM2_A1OePWM-2 Output A
OUTPUTXBAR15OOutput X-BAR Output 1
PMBUSA_SDA6I/ODPMBus-A Open-Drain Bidirectional Data
SPIA_SIMO7I/OSPI-A Slave In, Master Out (SIMO)
SCIA_TX9OSCI-A Transmit Data
FSIRXA_D110IFSIRX-A Data Input 1
I2CB_SDA11I/ODI2C-B Open-Drain Bidirectional Data
HIC_A113IHIC Address 1
CANA_TX14OCAN-A Transmit
HIC_D915I/OHIC Data 9
GPIO30, 4, 8, 12604939I/OGeneral-Purpose Input Output 3
EPWM2_B1OePWM-2 Output B
OUTPUTXBAR22, 5OOutput X-BAR Output 2
PMBUSA_SCL6I/ODPMBus-A Open-Drain Bidirectional Clock
SPIA_CLK7I/OSPI-A Clock
SCIA_RX9ISCI-A Receive Data
FSIRXA_D010IFSIRX-A Data Input 0
I2CB_SCL11I/ODI2C-B Open-Drain Bidirectional Clock
HIC_NOE13OHIC Output Enable
CANA_RX14ICAN-A Receive
HIC_D415I/OHIC Data 4
GPIO40, 4, 8, 12594838I/OGeneral-Purpose Input Output 4
EPWM3_A1OePWM-3 Output A
OUTPUTXBAR35OOutput X-BAR Output 3
CANA_TX6OCAN-A Transmit
SPIB_CLK7I/OSPI-B Clock
EQEP2_STROBE9I/OeQEP-2 Strobe
FSIRXA_CLK10IFSIRX-A Input Clock
CLB_OUTPUTXBAR611OCLB Output X-BAR Output 6
HIC_BASESEL213IHIC Base Address Range Select 2
HIC_NWE15IHIC Data Write Enable
GPIO50, 4, 8, 12746147I/OGeneral-Purpose Input Output 5
EPWM3_B1OePWM-3 Output B
OUTPUTXBAR33OOutput X-BAR Output 3
CANA_RX6ICAN-A Receive
SPIA_STE7I/OSPI-A Slave Transmit Enable (STE)
FSITXA_D19OFSITX-A Data Output 1
CLB_OUTPUTXBAR510OCLB Output X-BAR Output 5
HIC_A713IHIC Address 7
HIC_D414I/OHIC Data 4
HIC_D1515I/OHIC Data 15
GPIO60, 4, 8, 12806448I/OGeneral-Purpose Input Output 6
EPWM4_A1OePWM-4 Output A
OUTPUTXBAR42OOutput X-BAR Output 4
SYNCOUT3OExternal ePWM Synchronization Pulse
EQEP1_A5IeQEP-1 Input A
SPIB_SOMI7I/OSPI-B Slave Out, Master In (SOMI)
FSITXA_D09OFSITX-A Data Output 0
FSITXA_D111OFSITX-A Data Output 1
HIC_NBE113IHIC Byte Enable 1
CLB_OUTPUTXBAR814OCLB Output X-BAR Output 8
HIC_D1415I/OHIC Data 14
GPIO70, 4, 8, 12685743I/OGeneral-Purpose Input Output 7
EPWM4_B1OePWM-4 Output B
OUTPUTXBAR53OOutput X-BAR Output 5
EQEP1_B5IeQEP-1 Input B
SPIB_SIMO7I/OSPI-B Slave In, Master Out (SIMO)
FSITXA_CLK9OFSITX-A Output Clock
CLB_OUTPUTXBAR210OCLB Output X-BAR Output 2
HIC_A613IHIC Address 6
HIC_D1415I/OHIC Data 14
GPIO80, 4, 8, 125847I/OGeneral-Purpose Input Output 8
EPWM5_A1OePWM-5 Output A
ADCSOCAO3OADC Start of Conversion A for External ADC
EQEP1_STROBE5I/OeQEP-1 Strobe
SCIA_TX6OSCI-A Transmit Data
SPIA_SIMO7I/OSPI-A Slave In, Master Out (SIMO)
I2CA_SCL9I/ODI2C-A Open-Drain Bidirectional Clock
FSITXA_D110OFSITX-A Data Output 1
CLB_OUTPUTXBAR511OCLB Output X-BAR Output 5
HIC_A013IHIC Address 0
FSITXA_TDM_CLK14IFSITX-A Time Division Multiplexed Clock Input
HIC_D815I/OHIC Data 8
GPIO90, 4, 8, 127562I/OGeneral-Purpose Input Output 9
EPWM5_B1OePWM-5 Output B
OUTPUTXBAR63OOutput X-BAR Output 6
EQEP1_INDEX5I/OeQEP-1 Index
SCIA_RX6ISCI-A Receive Data
SPIA_CLK7I/OSPI-A Clock
FSITXA_D010OFSITX-A Data Output 0
LINB_RX11ILIN-B Receive
HIC_BASESEL013IHIC Base Address Range Select 0
I2CB_SCL14I/ODI2C-B Open-Drain Bidirectional Clock
HIC_NRDY15OHIC Ready
GPIO100, 4, 8, 127663I/OGeneral-Purpose Input Output 10
EPWM6_A1OePWM-6 Output A
ADCSOCBO3OADC Start of Conversion B for External ADC
EQEP1_A5IeQEP-1 Input A
SPIA_SOMI7I/OSPI-A Slave Out, Master In (SOMI)
I2CA_SDA9I/ODI2C-A Open-Drain Bidirectional Data
FSITXA_CLK10OFSITX-A Output Clock
LINB_TX11OLIN-B Transmit
HIC_NWE13IHIC Data Write Enable
FSITXA_TDM_D014IFSITX-A Time Division Multiplexed Data Input
GPIO110, 4, 8, 123731I/OGeneral-Purpose Input Output 11
EPWM6_B1OePWM-6 Output B
OUTPUTXBAR73OOutput X-BAR Output 7
EQEP1_B5IeQEP-1 Input B
SPIA_STE7I/OSPI-A Slave Transmit Enable (STE)
FSIRXA_D19IFSIRX-A Data Input 1
LINB_RX10ILIN-B Receive
EQEP2_A11IeQEP-2 Input A
SPIA_SIMO13I/OSPI-A Slave In, Master Out (SIMO)
HIC_D614I/OHIC Data 6
HIC_NBE015IHIC Byte Enable 0
GPIO120, 4, 8, 12363024I/OGeneral-Purpose Input Output 12
EPWM7_A1OePWM-7 Output A
EQEP1_STROBE5I/OeQEP-1 Strobe
PMBUSA_CTL7I/OPMBus-A Control Signal - Slave Input/Master Output
FSIRXA_D09IFSIRX-A Data Input 0
LINB_TX10OLIN-B Transmit
SPIA_CLK11I/OSPI-A Clock
CANA_RX13ICAN-A Receive
HIC_D1314I/OHIC Data 13
HIC_INT15OHIC Device Interrupt
GPIO130, 4, 8, 12352923I/OGeneral-Purpose Input Output 13
EPWM7_B1OePWM-7 Output B
EQEP1_INDEX5I/OeQEP-1 Index
PMBUSA_ALERT7I/ODPMBus-A Open-Drain Bidirectional Alert
FSIRXA_CLK9IFSIRX-A Input Clock
LINB_RX10ILIN-B Receive
SPIA_SOMI11I/OSPI-A Slave Out, Master In (SOMI)
CANA_TX13OCAN-A Transmit
HIC_D1114I/OHIC Data 11
HIC_D515I/OHIC Data 5
GPIO140, 4, 8, 1279I/OGeneral-Purpose Input Output 14
I2CB_SDA5I/ODI2C-B Open-Drain Bidirectional Data
OUTPUTXBAR36OOutput X-BAR Output 3
PMBUSA_SDA7I/ODPMBus-A Open-Drain Bidirectional Data
SPIB_CLK9I/OSPI-B Clock
EQEP2_A10IeQEP-2 Input A
LINB_TX11OLIN-B Transmit
EPWM3_A13OePWM-3 Output A
CLB_OUTPUTXBAR714OCLB Output X-BAR Output 7
HIC_D1515I/OHIC Data 15
GPIO150, 4, 8, 1278I/OGeneral-Purpose Input Output 15
I2CB_SCL5I/ODI2C-B Open-Drain Bidirectional Clock
OUTPUTXBAR46OOutput X-BAR Output 4
PMBUSA_SCL7I/ODPMBus-A Open-Drain Bidirectional Clock
SPIB_STE9I/OSPI-B Slave Transmit Enable (STE)
EQEP2_B10IeQEP-2 Input B
LINB_RX11ILIN-B Receive
EPWM3_B13OePWM-3 Output B
CLB_OUTPUTXBAR614OCLB Output X-BAR Output 6
HIC_D1215I/OHIC Data 12
GPIO160, 4, 8, 12393326I/OGeneral-Purpose Input Output 16
SPIA_SIMO1I/OSPI-A Slave In, Master Out (SIMO)
OUTPUTXBAR73OOutput X-BAR Output 7
EPWM5_A5OePWM-5 Output A
SCIA_TX6OSCI-A Transmit Data
EQEP1_STROBE9I/OeQEP-1 Strobe
PMBUSA_SCL10I/ODPMBus-A Open-Drain Bidirectional Clock
XCLKOUT11OExternal Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
EQEP2_B13IeQEP-2 Input B
SPIB_SOMI14I/OSPI-B Slave Out, Master In (SOMI)
HIC_D115I/OHIC Data 1
GPIO170, 4, 8, 124034I/OGeneral-Purpose Input Output 17
SPIA_SOMI1I/OSPI-A Slave Out, Master In (SOMI)
OUTPUTXBAR83OOutput X-BAR Output 8
EPWM5_B5OePWM-5 Output B
SCIA_RX6ISCI-A Receive Data
EQEP1_INDEX9I/OeQEP-1 Index
PMBUSA_SDA10I/ODPMBus-A Open-Drain Bidirectional Data
CANA_TX11OCAN-A Transmit
HIC_D215I/OHIC Data 2
GPIO18_X20, 4, 8, 12504133I/OGeneral-Purpose Input Output 18_X2
SPIA_CLK1I/OSPI-A Clock
CANA_RX3ICAN-A Receive
EPWM6_A5OePWM-6 Output A
I2CA_SCL6I/ODI2C-A Open-Drain Bidirectional Clock
EQEP2_A9IeQEP-2 Input A
PMBUSA_CTL10I/OPMBus-A Control Signal - Slave Input/Master Output
XCLKOUT11OExternal Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.
LINB_TX13OLIN-B Transmit
FSITXA_TDM_CLK14IFSITX-A Time Division Multiplexed Clock Input
HIC_INT15OHIC Device Interrupt
X2ALTOCrystal oscillator output. For more information about the ALT functionality, see the table that is in the External Oscillator (XTAL) section of the System Control chapter in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
GPIO19_X10, 4, 8, 12514234I/OGeneral-Purpose Input Output 19_X1
SPIA_STE1I/OSPI-A Slave Transmit Enable (STE)
CANA_TX3OCAN-A Transmit
EPWM6_B5OePWM-6 Output B
I2CA_SDA6I/ODI2C-A Open-Drain Bidirectional Data
EQEP2_B9IeQEP-2 Input B
PMBUSA_ALERT10I/ODPMBus-A Open-Drain Bidirectional Alert
CLB_OUTPUTXBAR111OCLB Output X-BAR Output 1
LINB_RX13ILIN-B Receive
FSITXA_TDM_D014IFSITX-A Time Division Multiplexed Data Input
HIC_NBE015IHIC Byte Enable 0
X1ALTICrystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. For more information about the ALT functionality, see the table that is in the External Oscillator (XTAL) section of the System Control chapter in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
GPIO220, 4, 8, 126756I/OGeneral-Purpose Input Output 22
EQEP1_STROBE1I/OeQEP-1 Strobe
SPIB_CLK6I/OSPI-B Clock
LINA_TX9OLIN-A Transmit
CLB_OUTPUTXBAR110OCLB Output X-BAR Output 1
LINB_TX11OLIN-B Transmit
HIC_A513IHIC Address 5
EPWM4_A14OePWM-4 Output A
HIC_D1315I/OHIC Data 13
GPIO230, 4, 8, 126554I/OGeneral-Purpose Input Output 23
EQEP1_INDEX1I/OeQEP-1 Index
SPIB_STE6I/OSPI-B Slave Transmit Enable (STE)
LINA_RX9ILIN-A Receive
LINB_RX11ILIN-B Receive
HIC_A313IHIC Address 3
EPWM4_B14OePWM-4 Output B
HIC_D1115I/OHIC Data 11
GPIO240, 4, 8, 12413527I/OGeneral-Purpose Input Output 24
OUTPUTXBAR11OOutput X-BAR Output 1
EQEP2_A2IeQEP-2 Input A
SPIB_SIMO6I/OSPI-B Slave In, Master Out (SIMO)
LINB_TX9OLIN-B Transmit
PMBUSA_SCL10I/ODPMBus-A Open-Drain Bidirectional Clock
SCIA_TX11OSCI-A Transmit Data
ERRORSTS13OError Status Output. When used, this signal requires an external pulldown.
HIC_D315I/OHIC Data 3
GPIO250, 4, 8, 1242I/OGeneral-Purpose Input Output 25
OUTPUTXBAR21OOutput X-BAR Output 2
EQEP2_B2IeQEP-2 Input B
EQEP1_A5IeQEP-1 Input A
SPIB_SOMI6I/OSPI-B Slave Out, Master In (SOMI)
FSITXA_D19OFSITX-A Data Output 1
PMBUSA_SDA10I/ODPMBus-A Open-Drain Bidirectional Data
SCIA_RX11ISCI-A Receive Data
HIC_BASESEL014IHIC Base Address Range Select 0
GPIO260, 4, 8, 1243I/OGeneral-Purpose Input Output 26
OUTPUTXBAR31, 5OOutput X-BAR Output 3
EQEP2_INDEX2I/OeQEP-2 Index
SPIB_CLK6I/OSPI-B Clock
FSITXA_D09OFSITX-A Data Output 0
PMBUSA_CTL10I/OPMBus-A Control Signal - Slave Input/Master Output
I2CA_SDA11I/ODI2C-A Open-Drain Bidirectional Data
HIC_D014I/OHIC Data 0
HIC_A115IHIC Address 1
GPIO270, 4, 8, 1244I/OGeneral-Purpose Input Output 27
OUTPUTXBAR41, 5OOutput X-BAR Output 4
EQEP2_STROBE2I/OeQEP-2 Strobe
SPIB_STE6I/OSPI-B Slave Transmit Enable (STE)
FSITXA_CLK9OFSITX-A Output Clock
PMBUSA_ALERT10I/ODPMBus-A Open-Drain Bidirectional Alert
I2CA_SCL11I/ODI2C-A Open-Drain Bidirectional Clock
HIC_D114I/OHIC Data 1
HIC_A415IHIC Address 4
GPIO280, 4, 8, 12422I/OGeneral-Purpose Input Output 28
SCIA_RX1ISCI-A Receive Data
EPWM7_A3OePWM-7 Output A
OUTPUTXBAR55OOutput X-BAR Output 5
EQEP1_A6IeQEP-1 Input A
EQEP2_STROBE9I/OeQEP-2 Strobe
LINA_TX10OLIN-A Transmit
SPIB_CLK11I/OSPI-B Clock
ERRORSTS13OError Status Output. When used, this signal requires an external pulldown.
I2CB_SDA14I/ODI2C-B Open-Drain Bidirectional Data
HIC_NOE15OHIC Output Enable
GPIO290, 4, 8, 12311I/OGeneral-Purpose Input Output 29
SCIA_TX1OSCI-A Transmit Data
EPWM7_B3OePWM-7 Output B
OUTPUTXBAR65OOutput X-BAR Output 6
EQEP1_B6IeQEP-1 Input B
EQEP2_INDEX9I/OeQEP-2 Index
LINA_RX10ILIN-A Receive
SPIB_STE11I/OSPI-B Slave Transmit Enable (STE)
ERRORSTS13OError Status Output. When used, this signal requires an external pulldown.
I2CB_SCL14I/ODI2C-B Open-Drain Bidirectional Clock
HIC_NCS15IHIC Chip Select
GPIO300, 4, 8, 121I/OGeneral-Purpose Input Output 30
CANA_RX1ICAN-A Receive
SPIB_SIMO3I/OSPI-B Slave In, Master Out (SIMO)
OUTPUTXBAR75OOutput X-BAR Output 7
EQEP1_STROBE6I/OeQEP-1 Strobe
FSIRXA_CLK9IFSIRX-A Input Clock
EPWM1_A11OePWM-1 Output A
HIC_D814I/OHIC Data 8
GPIO310, 4, 8, 122I/OGeneral-Purpose Input Output 31
CANA_TX1OCAN-A Transmit
SPIB_SOMI3I/OSPI-B Slave Out, Master In (SOMI)
OUTPUTXBAR85OOutput X-BAR Output 8
EQEP1_INDEX6I/OeQEP-1 Index
FSIRXA_D19IFSIRX-A Data Input 1
EPWM1_B11OePWM-1 Output B
HIC_D1014I/OHIC Data 10
GPIO320, 4, 8, 12494032I/OGeneral-Purpose Input Output 32
I2CA_SDA1I/ODI2C-A Open-Drain Bidirectional Data
SPIB_CLK3I/OSPI-B Clock
LINA_TX6OLIN-A Transmit
FSIRXA_D09IFSIRX-A Data Input 0
CANA_TX10OCAN-A Transmit
ADCSOCBO13OADC Start of Conversion B for External ADC
HIC_INT15OHIC Device Interrupt
GPIO330, 4, 8, 12383225I/OGeneral-Purpose Input Output 33
I2CA_SCL1I/ODI2C-A Open-Drain Bidirectional Clock
SPIB_STE3I/OSPI-B Slave Transmit Enable (STE)
OUTPUTXBAR45OOutput X-BAR Output 4
LINA_RX6ILIN-A Receive
FSIRXA_CLK9IFSIRX-A Input Clock
CANA_RX10ICAN-A Receive
EQEP2_B11IeQEP-2 Input B
ADCSOCAO13OADC Start of Conversion A for External ADC
HIC_D015I/OHIC Data 0
GPIO340, 4, 8, 1277I/OGeneral-Purpose Input Output 34
OUTPUTXBAR11OOutput X-BAR Output 1
PMBUSA_SDA6I/ODPMBus-A Open-Drain Bidirectional Data
HIC_NBE113IHIC Byte Enable 1
I2CB_SDA14I/ODI2C-B Open-Drain Bidirectional Data
HIC_D915I/OHIC Data 9
GPIO350, 4, 8, 12483931I/OGeneral-Purpose Input Output 35
SCIA_RX1ISCI-A Receive Data
I2CA_SDA3I/ODI2C-A Open-Drain Bidirectional Data
CANA_RX5ICAN-A Receive
PMBUSA_SCL6I/ODPMBus-A Open-Drain Bidirectional Clock
LINA_RX7ILIN-A Receive
EQEP1_A9IeQEP-1 Input A
PMBUSA_CTL10I/OPMBus-A Control Signal - Slave Input/Master Output
HIC_NWE14IHIC Data Write Enable
TDI15IJTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input.
GPIO370, 4, 8, 12463729I/OGeneral-Purpose Input Output 37
OUTPUTXBAR21OOutput X-BAR Output 2
I2CA_SCL3I/ODI2C-A Open-Drain Bidirectional Clock
SCIA_TX5OSCI-A Transmit Data
CANA_TX6OCAN-A Transmit
LINA_TX7OLIN-A Transmit
EQEP1_B9IeQEP-1 Input B
PMBUSA_ALERT10I/ODPMBus-A Open-Drain Bidirectional Alert
HIC_NRDY14OHIC Ready
TDO15OJTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input.
GPIO390, 4, 8, 125646I/OGeneral-Purpose Input Output 39
FSIRXA_CLK7IFSIRX-A Input Clock
EQEP2_INDEX9I/OeQEP-2 Index
CLB_OUTPUTXBAR211OCLB Output X-BAR Output 2
SYNCOUT13OExternal ePWM Synchronization Pulse
EQEP1_INDEX14I/OeQEP-1 Index
HIC_D715I/OHIC Data 7
GPIO400, 4, 8, 126453I/OGeneral-Purpose Input Output 40
SPIB_SIMO1I/OSPI-B Slave In, Master Out (SIMO)
EPWM2_B5OePWM-2 Output B
PMBUSA_SDA6I/ODPMBus-A Open-Drain Bidirectional Data
FSIRXA_D07IFSIRX-A Data Input 0
EQEP1_A10IeQEP-1 Input A
LINB_TX11OLIN-B Transmit
HIC_NBE114IHIC Byte Enable 1
HIC_D515I/OHIC Data 5
GPIO410, 4, 8, 126655I/OGeneral-Purpose Input Output 41
EPWM2_A5OePWM-2 Output A
PMBUSA_SCL6I/ODPMBus-A Open-Drain Bidirectional Clock
FSIRXA_D17IFSIRX-A Data Input 1
EQEP1_B10IeQEP-1 Input B
LINB_RX11ILIN-B Receive
HIC_A413IHIC Address 4
SPIB_SOMI14I/OSPI-B Slave Out, Master In (SOMI)
HIC_D1215I/OHIC Data 12
GPIO420, 4, 8, 1257I/OGeneral-Purpose Input Output 42
LINA_RX2ILIN-A Receive
OUTPUTXBAR53OOutput X-BAR Output 5
PMBUSA_CTL5I/OPMBus-A Control Signal - Slave Input/Master Output
I2CA_SDA6I/ODI2C-A Open-Drain Bidirectional Data
EQEP1_STROBE10I/OeQEP-1 Strobe
CLB_OUTPUTXBAR311OCLB Output X-BAR Output 3
HIC_D214I/OHIC Data 2
HIC_A615IHIC Address 6
GPIO430, 4, 8, 1254I/OGeneral-Purpose Input Output 43
OUTPUTXBAR63OOutput X-BAR Output 6
PMBUSA_ALERT5I/ODPMBus-A Open-Drain Bidirectional Alert
I2CA_SCL6I/ODI2C-A Open-Drain Bidirectional Clock
EQEP1_INDEX10I/OeQEP-1 Index
CLB_OUTPUTXBAR411OCLB Output X-BAR Output 4
HIC_D314I/OHIC Data 3
HIC_A715IHIC Address 7
GPIO440, 4, 8, 1269I/OGeneral-Purpose Input Output 44
OUTPUTXBAR73OOutput X-BAR Output 7
EQEP1_A5IeQEP-1 Input A
FSITXA_CLK7OFSITX-A Output Clock
CLB_OUTPUTXBAR310OCLB Output X-BAR Output 3
HIC_D713I/OHIC Data 7
HIC_D515I/OHIC Data 5
GPIO450, 4, 8, 1273I/OGeneral-Purpose Input Output 45
OUTPUTXBAR83OOutput X-BAR Output 8
FSITXA_D07OFSITX-A Data Output 0
CLB_OUTPUTXBAR410OCLB Output X-BAR Output 4
HIC_D615I/OHIC Data 6
GPIO460, 4, 8, 126I/OGeneral-Purpose Input Output 46
LINA_TX3OLIN-A Transmit
FSITXA_D17OFSITX-A Data Output 1
HIC_NWE15IHIC Data Write Enable
GPIO610, 4, 8, 12I/OGeneral-Purpose Input Output 61
GPIO620, 4, 8, 12I/OGeneral-Purpose Input Output 62
GPIO630, 4, 8, 12I/OGeneral-Purpose Input Output 63
TEST, JTAG, AND RESET
FLT134I/OFlash test pin 1. Reserved for TI. Must be left unconnected.
FLT233I/OFlash test pin 2. Reserved for TI. Must be left unconnected.
TCK453628IJTAG test clock with internal pullup.
TMS473830I/OJTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. This device does not have a TRSTn pin. An external pullup resistor (recommended 2.2 kΩ) on the TMS pin to VDDIO should be placed on the board to keep JTAG in reset during normal operation.
XRSn533I/ODDevice Reset (in) and Watchdog Reset (out). During a power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRSn pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRSn and VDDIO. If a capacitor is placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. This pin is an open-drain output with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
POWER AND GROUND
VDD8, 31, 53, 714, 27, 44, 5936, 451.2-V Digital Logic Power Pins. See the Power Management Module (PMM) section for usage details.
VDDA2622183.3-V Analog Power Pins. Place a minimum 2.2-µF decoupling capacitor on each pin. See the Power Management Module (PMM) section for usage details.
VDDIO7, 32, 52, 7228, 43, 6035, 463.3-V Digital I/O Power Pins. See the Power Management Module (PMM) section for usage details.
VSS9, 30, 55, 705, 26, 45, 5822, 37, 44Digital Ground
VSSA252117Analog Ground